User`s manual

Functional Overview
2.3.3 SRAM
Rev.1.01 Jan 31, 2008
2-7
REJ10J1262-0101
2
2.3.3 SRAM
The M3A-HS11 includes the 2-Mbyte SRAM as standard equipment. The SRAM is controlled by the bus state
controller included in SH7211.
Table2.3.3 lists the specification outline of SRAM. Figure 2.3.3 shows the block diagram of SH7211 and SRAM.
Table2.3.3 SRAM Specification Outline
Part Number Bus Size Capacity Package
R1LV1616RSA-7S 16-bit 2-Mbyte (16-bit × 1M word × 1 pc.) 48-pin TSOP (20 ×12mm)
SH7211
CS4
RD
RD/WR
16M-bit SRAM
(1M Word ×16bit)
20
16
BYTE#
CS1#
OE#
WE#
UB#
LB#
Reset
A19 - A0
A20 - A1
DQ15 - DQ0D15 - D0
WE1
WE0
CS2
3.3V
R1LV1616RSA-7
Figure 2.3.3 Block Diagram of SH7211 and SRAM