User`s manual

Functional Overview
2.3 Memory
Rev.1.01 Jan 31, 2008
2-6
REJ10J1262-0101
2
Figure 2.3.2 shows an example of SDRAM single read/write timing for operation that the SH7211 bus clock is
operating at 40 MHz.
CKIO
CKE
CS3
RASL
CASL
RDWR
DQMUU-
LL
MA0-9,11
MA10
BA0-1
D0-15
tcyc
(25ns)
ACT READA DESEL DESEL DESEL ACT WRITA DESEL DESEL
tSI
Tr
Tc1
Tcw
Td1
Tde
tCSD
SDRAM SINGLE READ
Tr Tc1 Trwl1 Trwl2
SDRAM SINGLE WRITE
tRC
tRCD
tRAS
tRCD
tRAS
tRC
tDQMD1
tAD1
tAD1
tAD1
tSI
tSI
tCASD
tHI
tCASD
tSI
tRASD
tHI
tRASD
tAD1
tSI
tHI
tAD1
Data
tAC
tRDS2
tRDH2
tOH
tHI
tCSD
tHI
tDQMD1
tDQMD1
tSI
tAD1
tSI
tCSD
tSI
tRASD
tHI
tRASD
tRP
tSI
tCASD
tHI
tCASD
tSI
tRWD
tHI
tRWD
tHI
tDQMD1
tAD1
tSI
tHI
tAD1
tWDD
2
tSI
tHI
tWDH2
tHI
tCSD
tDPL tRP
tDAL
Figure 2.3.2 Example of SDRAM Single Read/Write Timing