User`s manual
Functional Overview
2.3 Memory
Rev.1.01
Jan 31, 2008
2-5
REJ10J1262-0101
2
Table 2.3.2 lists the setting examples of bus state controller when the SH7211 bus clock is operating at 40 MHz.
Table 2.3.2 Setting Examples of Bus State Controller (CS3 Space)
User Area Target Device SDRAM Controller Setting
CS3 EDS1216AATA-75E CS3 Space Bus Control Register(CS3BCR)
Initial value: H'36DB 0600, Recommended set value: H'1000 4400
-
Idle cycles between write-read cycles and write-write cycles
IWW[2:0] = 001; 1
idle cycle inserted
- Memory type
TYPE[2:0] = 100; SDRAM
- Data bus size
BSZ[1:0] = 10; 16-bit size
CS3 Space Wait Control Register(CS3WCR)
Initial value: H'0000 0500, Recommended set value: H'0000 0000 0091
- Wait precharge completion cycle count
WTRP[1:0] = 00; No wait cycle
- Number of wait cycles from ACTV to READ/WRIT command
WTRCD[1:0] = 00; No wait cycle
- Area 3 CAS latency
A3CL[1:0] = 01; 2 cycles
- Number of command cycle from WRIT(A) to auto-precharge/PRE
command
TRWL[1:0] = 10; 2 cycles
Number of command cycle from REF command/self-refresh release to
ACTV command
WTRC[1:0] =01; 3 cycles
SDRAM Control Register(SDCR)
Initial value: H'0000 0000, Recommended set value: H'0000 0809
- Refresh control
RFSH = 1; Refresh is performed
- Refresh control
RMODE = 0; Auto-refreshing
- Bank active mode
BACTV = 0; Auto-precharge mode
- Number of bits of row address for area3
A3ROW[1:0] = 01; 12 bits
- Number of bits of column address for area3
A3COL[1:0] = 01; 9 bits
Refresh Timer Control/Status Register(RTCSR)
Initial value : H'0000 0000, Recommended set value : H’A55A 0010
- Clock select
CKS[2:0] = 010 ;Bφ/16
- Refresh count
RRC[2:0] = 000 ; Once
Refresh Time Constant Register(RTCOR)
Initial value: H'0000 0000, Recommended set value : H'A55A 0027
*The refresh request interval when clock select is set to Bφ/16 is as follows.
1 cycle :400nsec(40 MHz/16 = 2.5 MHz)
Refresh request intervals in the SDRAM : 15.625µsec/time
15.625µsec /400nsec = 39(0x27) cycle / refresh counts