User`s manual

Functional Overview
2.3 Memory
Rev.1.01 Jan 31, 2008
2-4
REJ10J1262-0101
2
2.3 Memory
2.3.1 SH7211 On-Chip Memory
The SH7211 includes 512-Kbyte flash memory and 32-Kbyte RAM.
2.3.2 SDRAM
The M3A-HS11 mounts 16MB SDRAM as standard equipment. The SDRAM is controlled by the bus state
controller built into SH7211. Table2.3.1 lists the SDRAM specifications used in M3A-HS11. Figure 2.3.1 shows the
block diagram of SDRAM connection.
Table2.3.1 SDRAM Specifications
Specification Content
Part Number EDS1216AATA-75E
Configuration 16 Mbytes (16-bit bus width) x 1pc.
Capacity 16 Mbytes
Access Time 5.4ns
CAS Latency 2 (at 40 MHz bus clock)
Refresh Interval 4,096 refresh cycles every 64ms
Low Address A11- A0
Column Address A8 - A0
Number of Banks 4-bank operation controlled by BA0 and BA1
SH7211
CS3
DQMLU
DQMLL
CK
CKE
RD/WR
RASL
CASL
A14
A13
BA1
BA0
DQMU
CLK
DQML
CS#
RAS#
CKE
WE#
CAS
A11-A0
EDS1216AATA
(8M Word x 16bit)
BA1
BA0
DQ15-DQ0
DQMU
CLK
DQML
CS#
RAS#
CKE
WE#
CAS#
A11-A0
A12-A1
D15-D0
11
16
Figure 2.3.1 Block Diagram of SDRAM Connection