Specifications

RX62N Group Ethernet Transmit and Receive Settings
RMII_RX_ER RX_ER
RX62N
LAN8700i
RMII (Reduced Media Independent Interface)
RMII_TXD1
RMII_TXD0
RMII_TXD_EN
ET_MDC
ET_MDIO
RMII_RXD1
RMII_RXD0
REF50CK
RMII_CRS_DV
TXD1
TXD0
TXD_EN
MDC
MDIO
RXD1
RXD0
RX_CLK
CRS_DV
Figure 3.2 LAN8700i Connection Example (RMII)
3.2 16BProcedure for Accessing MII/RMII Registers
The procedure for accessing the internal MII/RMII registers of the Ethernet physical layer transceiver (PHY) is
described below.
The serial interface (Serial Management Interface) used to access the MII/RMII registers consists of MDC and MDIO
(both pin names used on the ETHERC side). MDC is the clock pin used for synchronization, and MDIO is the data I/O
pin. The states of the pins can be referenced or changed by means of the PHY interface register (PIR) of the ETHERC.
There are no control pins, so data must always be output in the format stipulated by the MII/RMII specification
(MII/RMII management frames). Figure 3.3 shows an MII/RMII management frame. The sample program executes Z0
output for one bit period in the IDLE state. The IEEE802.3 specification does not mention clock input, but it is provided
for safety because without it some physical layer transceiver (PHY) devices cannot connect properly.
The MII/RMII management frame I/O is performed in order in 1-bit units, starting from PRE. Figures 3.4 to 3.7
illustrate the I/O sequence for 1-bit units. Make sure that the MDC and MDIO I/O timing conform to the IEEE802.3
specification. Table 3.1 and figure 3.8 show the I/O timing as stipulated in the IEEE802.3 specification.
Access Type MII/RMII Management Frame
Item
Number of bits
Read
Write
PRE
32
1..1
1..1
ST
2
01
01
OP
2
10
01
PHYAD
5
00001
00001
REGAD
5
RRRRR
RRRRR
TA
2
Z0
10
DATA
16
D..D
D..D
IDLE
X
[Legend]
PRE : 32 consecutive 1s
ST : Write 01 to indicate the start of the frame.
OP : Write the code indicating the access type.
PHYAD : Write 0001 if the PHY address is 1 (sequential write starting with the MSB).
This value varies according to the PHY address.
REGAD : Write 0001 if the register address is 1 (sequential write starting with the MSB).
This value varies according to the PHY register address.
TA : Time for switching data transmission source on MII/RMII interface
(a) For write: Write 10.
(b) For read: Perform bus release (notation: Z0).
DATA : 16 bits of data. Sequentially write or read from MSB.
(a) For write: Write 16 bits of data.
(b) For read: Read 16 bits of data.
IDLE : Wait time until next MII management format input
(a) For write: Perform independent bus release (notation: X).
(b) For read: Bus already released during TA; control unnecessary.
⎯
⎯
Figure 3.3 MII/RMII Management Frame Format
R01AN0629EJ0101 Rev.1.01 Page 7 of 52
Mar 31, 2011