Specifications

RX62N Group Ethernet Transmit and Receive Settings
End
1
Yes
No
Yes
No
2
Return R_ETHER_ERROR
Write 0x47FF0F9F to the ETHERC/EDMAC status register (EESR) to clear
the transmit status.
Set the start address of the receive descriptor list in the receive descriptor
list start address register (RDLAR).
Set the start address of the transmit descriptor list in the transmit
descriptor list start address register (TDLAR).
Write 0x00000000 to the transmit/receive status copy enable register
(TRSCER) to disable updating of transmit and receive status information in
the relevant descriptors, TFS25 to TFS0 and RFS26 to RFS0.
Write 0x00000000 to the transmit FIFO threshold register (TFTR) to select
store and forward mode.
Write 0x00000707 to the FIFO depth register (FDR) to set the capacity of
the transmit and receive FIFOs to 2,048 bytes.
Write 0x00000001 to the receiving method control register (RMCR) to
select continuous reception.
Only applicable for little endian operation
Write 1 to the big/little endian mode bit in the
EDMAC mode register (EDMR) to select little
endian mode.
EDMAC settings
Set transmit/receive data to
little endian mode
PHY initialization
phy_init
Initialization
successful?
Auto-negotiation result
acquisition
Auto-negotiation
successful?
Figure 4.21 Ethernet API Processing Sequence of Sample Program (2)
R01AN0629EJ0101 Rev.1.01 Page 40 of 52
Mar 31, 2011