Specifications

RX62N Group Ethernet Transmit and Receive Settings
Start
Transmit/receive descriptor initialization
_eth_fifoInit
Open function
R_Ether_Open
Initial pointer setting for
transmit/receive descriptor
Reset ETHERC/EDMAC
Yes
No
i < 0x00000100?
i = 0
i + 1
Yes
No
Check MAC address
MAC address = 0?
1
MAC address register setting
Set MAC address register
Read MAC address
Initialize the transmit descriptor and receive descriptor.
Initialization of pointer variable for managing the current descriptor
Set the initial value of the start address of the transmit/receive descriptor list.
Software reset of ETHERC/EDMAC
Write 1 to the SWR bit in the EDMAC mode register (EDMR).
Wait because access to the registers of all Ethernet-related modules is
prohibited during the software reset issue duration (64 cycles).
Set the MAC address in the MAC address high register
(MAHR) and MAC address low register (MALR). The
sample program does not include code for processing when
the MAC address is set to 0. The user must add appropriate
program code for processing when the MAC address is set
to 0.
Write 0x00000037 to the ETHERC status register (ECSR) to clear the
ETHERC internal status.
Write 0x00000020 to the ETHERC interrupt permission register (ECSIPR) to
prohibit interrupt notification by reports from the ECSR register.
Set the receive frame length bits in the receive frame length register (RFLR)
to specify 1,518 bytes.
Set the inter packet gap bits in the IPG register (IPGR) to specify 96 bits.
ETHERC settings
Figure 4.20 Ethernet API Processing Sequence of Sample Program (1)
R01AN0629EJ0101 Rev.1.01 Page 39 of 52
Mar 31, 2011