Specifications

RX62N Group Ethernet Transmit and Receive Settings
R01AN0629EJ0101 Rev.1.01 Page 3 of 52
Mar 31, 2011
1.3 11BApplicable Conditions
• MCU: RX62N Group
• Evaluation board: Renesas Starter Kit +(product number: R0K5562N0C000BE)
• Operating frequencies:
Input clock: 12 MHz
System clock (ICLK): 96 MHz
Peripheral module clock (PCLK): 48 MHz
External bus clock (BCLK) and SDRAM clock (SDCLK): 24 MHz
• Operating mode: Single-chip mode
• Integrated development environment: Renesas Electronics High-performance Embedded Workshop,
Ver. 4.07.00.007
• C compiler: Renesas Electronics RX Family C/C++ Compiler, Ver. 1.00.00.001
• Compile options:
⎯ Big endian operation
-cpu=rx600 -endian=big -patch=rx610 -include="$(WORKSPDIR)\src\bsp","$(WORKSPDIR)\src\driver"
-output=obj="$(CONFIGDIR)\$(FILELEAF).obj" -debug –nologo
⎯ Little endian operation
-cpu=rx600 -patch=rx610 -include="$(WORKSPDIR)\src\bsp","$(WORKSPDIR)\src\driver"
-output=obj="$(CONFIGDIR)\$(FILELEAF).obj" -debug –nologo
• Optimizing linkage editor: Renesas Electronics Optimizing Linkage Editor, Ver. 10.00.00.001
• Linker options:
-noprelink -rom=D=R,D_1=R_1,D_2=R_2 -nomessage -list="$(CONFIGDIR)\$(PROJECTNAME).map"
-show=all -nooptimize
-start=B_RX_DESC,B_TX_DESC,B_RX_BUFF_1,B_TX_BUFF_1,B_1,R_1,B_2,R_2, B,R,SU,SI, BETH_BUFF/
01000,PResetPRG/0FFFF8000,C_1,C_2,C,C$*,D*,P,PIntPRG,W*/0FFFF8100, FIXEDVECT/0FFFFFFD0 -nologo
-output="$(CONFIGDIR)\$(PROJECTNAME).abs" -end -input="$(CONFIGDIR)\ $(PROJECTNAME).abs"
-form=stype -output="$(CONFIGDIR)\$(PROJECTNAME).mot" -exit