Specifications

RX62N Group Ethernet Transmit and Receive Settings
Yes
No
Yes
No
TACT = 0?
1
2
PHY initialization and link
• PHY initialization
Use the PIR register to reset the PHY.
• Auto-negotiation
Use the PIR register to start auto-negotiation by the PHY.
EDMAC settings
• Clear status
• Transmit/receive settings
PHY initialization and link
• PHY initialization
• Auto-negotiation
Auto-negotiation
complete?
Start reception
Enable transmission/reception
Enable interrupts
Set to connection mode supported
by link partner
• Clear status
Write 1 to flag bits in ETHERC/EDMAC status register (EESR) to clear them.
• Transmit/receive settings
Set the following registers/bit according to the operation settings:
Bits other than software reset (SWR) in EDMAC mode register (EDMR)
Transmit descriptor list start address register (TDLAR)
Receive descriptor list start address register (RDLAR)
Transmit/receive status copy enable register (TRSCER)
Transmit FIFO threshold register (TFTR)
FIFO depth register (FDR)
Receiving method control register (RMCR)
Flow control start FIFO threshold setting register (FCFTR)
Receive data padding insert register (RPADIR)
Transmit interrupt setting register (TRIMD)
Confirmation that operation using current descriptor is not underway
Using the descriptor management pointer for transmission,
confirm that the TACT bit of the current descriptor is cleared to 0,
indicating that transmission has completed or been aborted.
Wait for auto-negotiation to complete.
Set the duplex mode (DM) bit in the ETHERC mode register (ECMR)
to match the auto-negotiation result. For RMII,
set the transmission/reception rate (RTM) bit as well.
In the ETHERC interrupt permission register (ECSIPR) and
ETHERC/EDMAC status interrupt permission register (EESIPR)
set the bits for the interrupts to be used to 1 (enabled).
Set the IEN0 bit to 1 in interrupt request enable register 04 (IER04)
of the interrupt control unit (ICUa).
Set the priority level in interrupt priority register 08 (IPR08) of
the interrupt control unit (ICUa).
Set the transmit enable (TE) and receive enable (RE) bits
in the ETHERC mode register (ECMR) to 1 to enable transmission
and reception.
Set the receive request (RR) bit in the EDMAC receive request
register (EDRRR) to 1 to enable the receive function.
Figure 4.12 Sample Ethernet Transmit/Receive Setting Sequence (2)
R01AN0629EJ0101 Rev.1.01 Page 29 of 52
Mar 31, 2011