Specifications

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RX62N Group Ethernet Transmit and Receive Settings

4.1.12 42BFunction Operating Procedure (Transmission/Reception)

The basic settings needed for Ethernet transmission and reception are described below. Figures 4.11 to 4.13 show

sample Ethernet transmit/receive setting sequences.

Start

Reset ETHERC/EDMAC

ETHERC settings

• Clear status

• MAC address settings

• Transmit/receive settings

Descriptor settings

• Transmit/receive descriptor initial settings

• Clear transmit/receive buffer to 0

• Initial pointer setting in transmit/receive descriptor

Software reset of ETHERC/EDMAC

Write 1 to the SWR bit in the EDMAC mode register (EDMR).

Do not allow access to the registers of all Ethernet-related modules

during the software reset issue duration (64 cycles).

• Transmit/receive descriptor initial settings

TD0: (TACT) Set for frame transmission.

(TDLE) Set to 1 in last plane (and to 0 in other planes).

(TFP) Set for frame transmission.

(TWBI) Set to 1 in plane triggering write-back end interrupt.

TD1: (TBL) Set for frame transmission.

TD2: (TBA) Set to start address of transmit buffer corresponding to each descriptor.

The transmit buffer must be aligned with a 32-byte boundary.

Padding area: The EDMAC does not use this area. It may be set to any user-defined value.

RD0: (RACT) Set to 1 (active).

(RDLE) Set to 1 in last plane (and to 0 in other planes).

(RFP) No need to set. Manipulated by write-back by EDMAC.

RD1: (RBL) Set to maximum transfer byte length of receive buffer.

(RFL) No need to set. Manipulated by write-back by EDMAC.

RD2: (RBA) Set to start address of transmit buffer corresponding to each descriptor.

The receive buffer must be aligned with a 32-byte boundary.

Padding area: The EDMAC does not use this area. It may be set to any user-defined value.

• Clear transmit/receive buffer to 0

Clear transmit/receive data buffer area in memory to 0.

• Transmit/receive descriptor initial pointer setting

Initialize the pointer variable for managing the current descriptor.

Set the start address of the transmit/receive descriptor list to the initial value.

• Clear status

Write 1 to flag bits in ETHERC status register (ECSR) to clear them.

• MAC address settings

Set the upper 32 bits of the 48-bit MAC address in the MAC address high register (MAHR).

Set the lower 16 bits of the 48-bit MAC address in the MAC address low register (MALR).

• Transmit/receive settings

Set the following registers/bit according to the operation settings:

Bits other than transmit enable (TE) and receive enable (RE) in ETHERC mode register (ECMR)