Specifications

RX62N Group Ethernet Transmit and Receive Settings

4.1.11 41BFunction Operating Procedure (Reception)

The EDMAC receiver is activated when the receive request (RR) bit in the EDMAC receive request register

(EDRRR) is set to 1 while the value of the RE bit in ECMR is 1. After a software reset of the ETHERC and EDMAC,

the EDMAC reads the descriptor indicated by the receive descriptor list start address register (RDLAR) and, if the

RACT bit is set to 1 (active), enters the receive standby state. When the ETHERC receives a frame for a local

destination (an address for which local reception is enabled), it stores it in the receive FIFO. If the value of the RACT

bit in the receive descriptor is 1, the EDMAC transfers the frame to the receive buffer specified by RD2. (If the value of

the RACT bit is 0 (inactive), the RR bit is cleared to 0 and EDMAC receive operation stops.) If the data length of a

received frame is longer than the buffer length specified by RD1, the EDMAC performs a write-back operation to the

descriptor (RFP = B'10 or B'00) when the buffer becomes full, then reads the next descriptor. When frame reception is

completed, or if frame reception is aborted because of an error, the EDMAC performs write-back to the relevant

descriptor (RFP = B'11 or B'01).

When continuous reception is selected (receive request bit reset (RNR) bit in receiving method control register

(RMCR) set to 1), the EDMAC reads the next descriptor and, if the RACT bit is set to 1, enters the receive standby state.

When continuous reception is selected, setting the receive request bit non-reset mode (RNC) bit in the RMCR register

to 1 causes EDMAC receive operation to continue, with no clearing of the RR bit even if the RACT bit is cleared to 0

(inactive). (Receive descriptors are fetched consecutively, and receive frame DMA continues.) When continuous

reception is not selected (value of RNR bit in RMCR register is 0), the RR bit in the EDRRR register is cleared to 0 and

EDMAC receive operation ends. Setting the RR bit to 1 once again causes the EDMAC to read the next descriptor after

the descriptor from the last receive operation and then enter the receive standby state.

Figure 4.10 shows a sample reception sequence.

RX62N Group + memory

Reception sequence

EDMAC ETHERC

Receive

FIFO Ethernet

Reception end

Receive data transfer

Frame reception

ETHERC/EDMAC

initialization

Descriptor and

receive buffer

settings

Receive instruction

Descriptor read

(preparation for receiving

next frame)

Descriptor read

Descriptor write-back

Figure 4.10 Sample Reception Sequence (Single-Frame/Single-Descriptor)

R01AN0629EJ0101 Rev.1.01 Page 27 of 52

Mar 31, 2011