Specifications

RX62N Group Ethernet Transmit and Receive Settings
4.1.10 40BFunction Operating Procedure (Transmission)
The EDMAC transmitter is activated when the transmit request (TR) bit in the EDMAC transmit request register
(EDTRR) is set to 1 while the value of the TE bit in the ETHERC mode register (ECMR) is 1. After a software reset of
the ETHERC and EDMAC, the EDMAC reads the descriptor indicated by the transmit descriptor list start address
register (TDLAR). If the TACT bit of the descriptor that was read is set to 1 (active), the EDMAC sequentially reads
transmit frame data from the transmit buffer start address specified by TD2 for transfer to the ETHERC. The ETHERC
creates a transmit frame and starts transmission to the MII/RMII. After DMA transfer of data equivalent to the buffer
length specified in the descriptor, the processing described below is carried out according to the value of TFP.
• TFP = B'00 or B'10 (frame continuation)
Descriptor write-back (writing 0 to the TACT bit) is performed after DMA transfer. Then the TACT bit of the next
descriptor is read.
• TFP = B'01 or B'11 (frame end)
Descriptor write-back (writing 0 to the TACT bit and status bits) is performed after completion of frame
transmission. Then the TACT bit of the next descriptor is read.
When the TACT bit of the descriptor that was read is set to 1 (active), frame transmission continues and the next
descriptor is read. When a descriptor with the TACT bit cleared to 0 (inactive) is read, the EDMAC clears the TR bit in
EDTRR to 0 and transmit processing completes. Setting the TR bit to 1 after it has been cleared to 0 reactivates the
EDMAC transmitter, and in this case the next descriptor after the descriptor from the last transmission is read. Figure
4.9 shows a sample transmission sequence.
Transmission sequence
EDMAC ETHERC
Ethernet
ETHERC/EDMAC
initialization
Descriptor and
transmit buffer
settings
Transmit instruction
Descriptor write-back
Descriptor read
Transmit data transfer
Transmit data transfer
Frame transmission
Transmission end
Descriptor read
Descriptor write-back
RX62N Group + memory Transmit FIFO
Figure 4.9 Sample Transmission Sequence
R01AN0629EJ0101 Rev.1.01 Page 26 of 52
Mar 31, 2011