Specifications

RX62N Group Ethernet Transmit and Receive Settings
4.1.9 39BReceive Descriptor Setting Example
Figure 4.8 shows an example in which three receive descriptor planes and three receive buffer planes are used. Each
receive buffer can accommodate 1,536 bytes, and single-frame/single-descriptor operation is used. The figure is
abbreviated to show only the RD0 portion of each receive descriptor. The numbers (1), (2), etc., in the figure indicate
the execution sequence.
Settings are performed as follows.
• 1. Bits RFP1, RFP0, RFE, and RFS26 to RFS0 in all the descriptor planes are cleared to 0.
• 2. The RDLE bit in the first and second descriptor planes is cleared to 0. The RDLE bit in the third descriptor
plane is set to 1, which causes the first descriptor plane to be read after processing of the third descriptor plane
completes. These settings enable the descriptors to function in a ring configuration.
• 3. Though omitted from figure 4.8, before reception starts the receive buffer size is set to 1,536 bytes by the RBL
bits in RD1 of all the descriptor planes, and the receive buffer start address is specified by the RBA bits in RD2.
• 4. The RACT bit of all the descriptor planes is set to 1 for continuous reception. The reception procedure is
described in more detail in 4.1.11, Function Operating Procedure (Reception).
(1)
(2)
(3)
(4)
(5)
(6)
R
D
L
E
R
F
P
1
R
F
P
0
R
A
C
T
R
F
E
RFS26 to RFS0
000100
000100
10010
0
0
0
0
0
00
• •
• •
• •
1st plane
2nd plane
3rd plane
(Omitted)
(Omitted)
(Omitted)
Receive descriptors
Receive buffers
Figure 4.8 Correspondence of Receive Descriptors and Receive Buffers
R01AN0629EJ0101 Rev.1.01 Page 25 of 52
Mar 31, 2011