Specifications

RX62N Group Ethernet Transmit and Receive Settings
4.1.5 35BOverview of Descriptors
To perform a DMA transfer, the EDMAC requires a unit of data called a descriptor that contains information such as
the storage address of the transmit or receive data. There are two types of descriptors: transmit descriptors and receive
descriptors. The EDMAC automatically starts reading a transmit descriptor when the TR bit in the EDMAC transmit
request register (EDTRR) is set to 1, and when the RR bit in the EDMAC receive request register (EDRRR) is set to 1 it
automatically starts reading a receive descriptor. It is necessary for the user to declare beforehand in the transmit or
receive descriptor the appropriate information regarding the DMA transfer of the transmit or receive data. When
transmission or reception of an Ethernet frame completes, the EDMAC clears to 0 the descriptor’s active bit (TACT for
transmission and RACT for reception) and updates the status bits (TFS25 to TFS0 for transmission and RFS26 to RFS0
for reception) to reflect the transmit or receive result.
The descriptors are allocated to a readable memory space, and the address of the start descriptor (the first descriptor
read by the EDMAC) is specified in the transmit descriptor list start address register (TDLAR) or receive descriptor list
start address register (RDLAR). When preparing multiple descriptors in a descriptor list, allocate the descriptors to
consecutive addresses according to the descriptor length specified by the DL bits in the EDMAC mode register
(EDMR).
4.1.6 36BOverview of Transmit Descriptor
Figure 4.5 shows the correspondence between a transmit descriptor and a transmit buffer.
A transmit descriptor comprises, beginning from the start of the data, 32-bit units designated TD0, TD1, and TD2,
followed by padding. TD0 contains a bit indicating whether the transmit descriptor is active or inactive as well as
descriptor configuration information and status information. TD1 indicates the data length (TBL) of the transmit buffer
containing the data to be transferred according to the designation of the descriptor. TD2 indicates the start address of the
transmit buffer containing the data to be transferred. The length of the padding is determined according to the descriptor
length specified by the DL bits in the EDMR register.
Depending on the transmit descriptor settings, one descriptor can specify a single frame of transmit data (single-
frame/single-descriptor) or multiple descriptors can specify a single frame of transmit data (single-frame/multi-
descriptor). Single-frame/multi-descriptor operation can be used, for example, to set multiple descriptors to specify a
fixed portion of data that is transmitted in every Ethernet frame. Specifically, the data in each Ethernet frame specifying
the destination address and transmit source address could be shared in common by multiple descriptors and the
remaining data stored in its own buffer.
Valid transmit data
T
A
C
T
TFSTD0
TBLTD1
TBA
Padding (4, 20, or 52 bytes)
TD2
31
30 29 28 27 26 0
31
31
16
0
T
W
B
I
T
F
E
T
D
L
E
T
F
P
1
T
F
P
0
Note: The padding is a redundant area whose size is adjusted according to the descriptor length
(16, 32, or 64 bytes).
Transmit descriptor Transmit buffer
Figure 4.5 Correspondence of Transmit Descriptor and Transmit Buffer
R01AN0629EJ0101 Rev.1.01 Page 22 of 52
Mar 31, 2011