Specifications

RX62N Group Ethernet Transmit and Receive Settings
4.1.4 34BOverview of EDMAC
The RX62N Group has an on-chip direct memory access controller (EDMAC) that is directly connected to the
Ethernet controller (ETHERC). Most buffer management is controlled by the EDMAC by using descriptors. This
reduces the load on the CPU, enabling efficient data transmission and reception.
The EDMAC is connected to the ETHERC, allowing efficient transfer of transmit and receive data to and from the
memory (buffers), bypassing the CPU. The EDMAC itself reads stored control information, such as buffer pointers
(called descriptors) that correspond to the individual buffers. Transmit data is read from the transmit buffers, and
receive data written to the receive buffers, according to the control information. By arranging multiple descriptors
consecutively (in a descriptor list), transmission and reception can be performed continuously.
Table 4.1 lists the EDMAC specifications, and figure 4.4 shows the configuration of the EDMAC and of the
descriptors and transmit/receive buffers in memory.
Table 4.1 Specifications of EDMAC
Item Description
Data transmission and reception
• Descriptor management system
• Support for single-frame/multi-buffer operation
Functions
• Efficient system bus utilization through use of DMA block transfer
(32-byte units)
• Indication in descriptors of transmit/receive frame status information
• Ability to insert padding in receive data
EDMAC
ETHERC
Transmit FIFO
Receive FIFO
Transmit
descriptors
Descriptor
information
Transmit DMAC
Descriptor
information
Receive DMAC
Transmit buffers
Receive buffers
External memory
Receive
descriptors
RX62N Group
External
bus
interface
Internal bus
Internal
bus
interface
Figure 4.4 Configuration of EDMAC, Descriptors, and Buffers
R01AN0629EJ0101 Rev.1.01 Page 21 of 52
Mar 31, 2011