Specifications

RX62N Group Ethernet Transmit and Receive Settings
Start
Write 0x00000002 to PIR register
1-bit (value: 0) output function
_phy_mii_write_0
End
MDC wait OK?
Yes
No
Write 0x00000003 to PIR register
MDC wait OK?
Yes
No
Write 0x00000003 to PIR register
MDC wait OK?
Yes
No
MDC wait OK?
Yes
No
Write 0x00000002 to PIR register
The MDC wait is defined as MDC_WAIT.
MDC_WAIT is defined in phy.h.
Output low-level from ET_MDC pin.
Set ET_MDIO pin to write direction and output low-level.
Output high-level from ET_MDC pin.
Output low-level from ET_MDIO pin.
Output high-level from ET_MDC pin.
Output low-level from ET_MDIO pin.
Output low-level from ET_MDC pin.
Output low-level from ET_MDIO pin.
Figure 3.17 Processing Sequence of MII/RMII Register Access (7)
3.4 18BDetails of Physical Layer Transceiver (PHY) Auto-Negotiation Settings
Table 3.2 lists the settings used in the sample program.
Table 3.2 Sample Program Settings
Item Description
PHY model LAN8700i from Standard Microsystems Corporation
Link modes 100 Mbps (full-duplex, half-duplex) and 10 Mbps (full-duplex, half-duplex)
Link determination method Auto-negotiation
PHY address
0x1F*
1
Setting target MII/RMII
registers
Register 0 — Basic Control (address: 0x00)
Register 1 — Basic Status (address: 0x01)
Register 4 — Auto Negotiation Advertisement (address: 0x04)
Register 5 — Auto Negotiation Link Partner Ability (address: 0x05)
Note: 1. The setting of the Renesas Starter Kit +(product number: R0K5562N0C000BE) is 0x1F. This must
be changed to match the actual PHY address.
R01AN0629EJ0101 Rev.1.01 Page 16 of 52
Mar 31, 2011