Specifications

RX62N Group Ethernet Transmit and Receive Settings
Yes
No
Output 1 bit (value: 0)
_phy_mii_write_0()
Output 1 bit (value: 1)
_phy_mii_write_1()
Start
Data output function
_phy_reg_write
End
Highest data bit = 0?
Shift data 1 to left
Output of 16 bits complete?
Yes
No
Figure 3.14 Processing Sequence of MII/RMII Register Access (4)
Yes
No
Write 0x00000001 to PIR register
Yes
No
Yes
No
Start
Write 0x00000000 to PIR register
Bus release function
_phy_ta_z0
End
MDC wait OK?
MDC wait OK?
Write 0x00000001 to PIR register
MDC wait OK?
MDC wait OK?
Yes
No
Write 0x00000000 to PIR register
The MDC wait is defined as MDC_WAIT.
MDC_WAIT is defined in phy.h.
Start
Output 1 bit (value: 1)
_phy_mii_write_1()
TA during write function
_phy_ta_10
End
Output 1 bit (value: 0)
_phy_mii_write_0()
Output low-level from ET_MDC pin.
Set ET_MDIO pin to read direction.
Output high-level from ET_MDC.
Output high-level from ET_MDC.
Output low-level from ET_MDC pin.
Figure 3.15 Processing Sequence of MII/RMII Register Access (5)
R01AN0629EJ0101 Rev.1.01 Page 14 of 52
Mar 31, 2011