Specifications

RX62N Group Ethernet Transmit and Receive Settings
End
Write 0x01E1 to MII/RMII register 4 to enable the following PHY link conditions:
full-duplex, half-duplex, 10 Mbps, 100 Mbps.
Read MII/RMII register 1.
Bit 5 in MII/RMII register 1 of the LAN8700i is read twice because the internal state is
reflected by a latch circuit.
Yes
No
No
Yes
Check the following two points:
• That bit 5 in the MII/RMII register is set to 1 (auto-negotiation completed)
• That the wait counter value does not exceed the maximum value
(PHY_AUTO_NEGOTIATION_WAIT) (timeout)
PHY_AUTO_NEGOTIATON_WAIT is defined in phy.h.
Start
Write to MII/RMII register 4
_phy_write()
Auto-negotiation result acquisition function
phy_set_autonegotiate
Read MII/RMII register 1
_phy_read()
Auto-negotiation not complete
and no timeout occurred?
Timeout occurred?
Return R_PHY_ERROR
Write to MII/RMII register 0
_phy_write()
Write 0x1200 to MII/RMII register 0 to start auto-negotiation.
Read MII/RMII register 5 and return result
_phy_read()
Read MII/RMII register 5 and return the connection modes
supported by the link partner.
Figure 3.10 Auto-Negotiation Result Acquisition Function
Bus release (transmit source switch)
Command output (read command)
Bus release (transmit source switch)
Start
Preamble output
_phy_preamble()
MII/RMII register read function
_phy_read
End
_phy_ta_z0()
_phy_reg_set()
DATA input
_phy_reg_read()
_phy_ta_z0()
Command output (write command)
Start
Preamble output
_phy_preamble()
MII/RMII register write function
_phy_write
End
Output 10
_phy_ta_10()
_phy_reg_set()
DATA output
_phy_reg_write()
Bus release (transmit source switch)
_phy_ta_z0()
Figure 3.11 Processing Sequence of MII/RMII Register Access (1)
R01AN0629EJ0101 Rev.1.01 Page 11 of 52
Mar 31, 2011