APPLICATION NOTE RX62N Group R01AN0629EJ0101 Rev.1.01 Mar 31, 2011 Ethernet Transmit and Receive Settings Introduction This application note presents a sample program that makes settings for transmitting and receiving Ethernet/IEEE802.3 frames using the Ethernet controller (ETHERC) and Ethernet DMA controller (EDMAC).
RX62N Group 1. Ethernet Transmit and Receive Settings Introduction 0B 1.1 Specifications 9B • The sample program supports the big endian and little endian operating modes of the RX62N. • The sample program supports the Media Independent Interface (MII) and Reduced Media Independent Interface (RMII). • The sample program does not include any interrupt handling functionality. In order to use interrupts, it is necessary for the customer to create the necessary program code separately.
RX62N Group 1.3 Ethernet Transmit and Receive Settings Applicable Conditions 1B • MCU: RX62N Group • Evaluation board: Renesas Starter Kit +(product number: R0K5562N0C000BE) • Operating frequencies: Input clock: 12 MHz System clock (ICLK): 96 MHz Peripheral module clock (PCLK): 48 MHz External bus clock (BCLK) and SDRAM clock (SDCLK): 24 MHz • Operating mode: Single-chip mode • Integrated development environment: Renesas Electronics High-performance Embedded Workshop, Ver. 4.07.00.
RX62N Group 2. Ethernet Transmit and Receive Settings Description of Initial Settings 1B An initial settings program, which performs minimal hardware initialization processing such as memory initialization after a power-on reset, is required in order to use the Ethernet driver of the sample program. Sample settings for the initial settings program are described below. 2.1 Description of Initial Settings Program 12B The initial settings program comprises multiple source files, including resetprg.
RX62N Group Ethernet Transmit and Receive Settings HardwareSetup function Start Clock generation circuit settings io_set_cpg() I/O port settings ConfigurePortPins() Module stop function setting EnablePeripheralModules() Set the system clock (ICLK), peripheral module clock (PCLK), external bus clock (BCLK), and SDRAM clock (SDCLK). Set the I/O ports to be used for Ethernet communication. Disable the module stop function for the Ethernet controller DMA controller (EDMAC). End Figure 2.
RX62N Group 3. Ethernet Transmit and Receive Settings Description of Physical Layer Transceiver (PHY) Auto-Negotiation Settings 2B The sample program uses the Ethernet physical layer transceiver (PHY) to perform auto-negotiation. The autonegotiation result is read via the PHY interface register (PIR) of the ETHERC. 3.1 Operation of Functions Used 15B The actual physical layer link processing is performed using the functionality of the Ethernet physical layer transceiver (PHY).
RX62N Group Ethernet Transmit and Receive Settings RMII (Reduced Media Independent Interface) LAN8700i RX62N RMII_TXD1 RMII_TXD0 RMII_TXD_EN TXD1 TXD0 TXD_EN ET_MDC ET_MDIO RMII_RXD1 RMII_RXD0 REF50CK RMII_CRS_DV MDC MDIO RXD1 RXD0 RX_CLK CRS_DV RMII_RX_ER RX_ER Figure 3.2 LAN8700i Connection Example (RMII) 3.2 Procedure for Accessing MII/RMII Registers 16B The procedure for accessing the internal MII/RMII registers of the Ethernet physical layer transceiver (PHY) is described below.
RX62N Group Ethernet Transmit and Receive Settings (1) Write to PHY interface register PIR.MMD = 1 PIR.MDO = write data PIR.MDC = 0 ET_MDC MDO (2) Write to PHY interface register (1) (2) (3) 1-bit data write timing relationship PIR.MMD = 1 PIR.MDO = write data PIR.MDC = 1 (3) Write to PHY interface register PIR.MMD = 1 PIR.MDO = write data PIR.MDC = 0 Figure 3.4 1-Bit Data Write Sequence (1) Write to PHY interface register ET_MDC PIR.MMD = 0 PIR.
RX62N Group Ethernet Transmit and Receive Settings (1) Write to PHY interface register ET_MDC PIR.MMD = 0 PIR.MDC = 1 MDI (2) Read from PHY interface register PIR.MMD = 0 PIR.MDC = 1 PIR.MDI is read data (1) (2) (3) 1-bit data read timing relationship (3) Write to PHY interface register PIR.MMD = 0 PIR.MDC = 0 Figure 3.6 1-Bit Data Read Sequence (1) Write to PHY interface register ET_MDC PIR.MMD = 0 PIR.MDC = 0 MDO (1) Independent bus release timing relationship Figure 3.
RX62N Group 3.3 Ethernet Transmit and Receive Settings Description of Physical Layer Transceiver (PHY) Auto-Negotiation Settings 17B • phy.c This file contains declarations for the function that initializes the physical layer transceiver (PHY) (phy_init function) and the function that obtains the auto-negotiation result (phy_set_autonegotiate function). Figure 3.9 shows the processing sequence of the phy_init function and figure 3.10 of the phy_set_autonegotiate function. Figures 3.11 to 3.
RX62N Group Ethernet Transmit and Receive Settings Auto-negotiation result acquisition function phy_set_autonegotiate Start Yes Write to MII/RMII register 4 _phy_write() Write 0x01E1 to MII/RMII register 4 to enable the following PHY link conditions: full-duplex, half-duplex, 10 Mbps, 100 Mbps. Write to MII/RMII register 0 _phy_write() Write 0x1200 to MII/RMII register 0 to start auto-negotiation. Read MII/RMII register 1 _phy_read() Read MII/RMII register 1.
RX62N Group Ethernet Transmit and Receive Settings Preamble output function _phy_preamble Command output function _phy_reg_set Start Start Set ST code (01) in command bits 15 and 14 1-bit output _phy_preamble() Set OP code (10 or 01) in command bits 13 and 12 No Set PHYAD code (xxxxx) in command bits 11 to 7 Output of 32 bits complete? Yes Set REGAD code (xxxxx) in command bits 6 to 2 End Highest command bit = 0? No Yes Output 1 bit (value: 0) _phy_mii_write_0() Output 1 bit (value: 1) _phy_
RX62N Group Ethernet Transmit and Receive Settings Data input function _phy_reg_read Start Write 0x00000000 to PIR register No MDC wait OK? Output low-level from ET_MDC pin. Set ET_MDIO pin to read direction. The MDC wait is defined as MDC_WAIT. MDC_WAIT is defined in phy.h. Yes Write 0x00000001 to PIR register Output high-level from ET_MDC. No MDC wait OK? Yes Read MDI bit in PIR register Write 0x00000001 to PIR register Output high-level from ET_MDC.
RX62N Group Ethernet Transmit and Receive Settings Data output function _phy_reg_write Start Highest data bit = 0? No Yes Output 1 bit (value: 0) _phy_mii_write_0() Output 1 bit (value: 1) _phy_mii_write_1() Shift data 1 to left No Output of 16 bits complete? Yes End Figure 3.14 Processing Sequence of MII/RMII Register Access (4) Bus release function _phy_ta_z0 TA during write function _phy_ta_10 Start Start Write 0x00000000 to PIR register Output low-level from ET_MDC pin.
RX62N Group Ethernet Transmit and Receive Settings 1-bit (value: 1) output function _phy_mii_write_1 Start Write 0x00000006 to PIR register No MDC wait OK? Output low-level from ET_MDC pin. Set ET_MDIO pin to write direction and output high-level. The MDC wait is defined as MDC_WAIT. MDC_WAIT is defined in phy.h. Yes Write 0x00000007 to PIR register No Output high-level from ET_MDC pin. Output high-level from ET_MDIO pin.
RX62N Group Ethernet Transmit and Receive Settings 1-bit (value: 0) output function _phy_mii_write_0 Start Write 0x00000002 to PIR register No MDC wait OK? Output low-level from ET_MDC pin. Set ET_MDIO pin to write direction and output low-level. The MDC wait is defined as MDC_WAIT. MDC_WAIT is defined in phy.h. Yes Write 0x00000003 to PIR register No Output high-level from ET_MDC pin. Output low-level from ET_MDIO pin.
RX62N Group 3.5 Ethernet Transmit and Receive Settings Notes on Physical Layer Transceiver (PHY) Auto-Negotiation Settings 19B • The sample program assumes that auto-negotiation mode is used as the PHY link determination method. • When the partner device is operating in auto-negotiation mode, the link mode is determined according to the priority levels shown in table 3.3. Table 3.
RX62N Group 4. Ethernet Transmit and Receive Settings Description of Transmit/Receive Settings 3B The sample program makes use of the Ethernet controller (ETHERC) and Ethernet controller direct memory access controller (EDMAC). 4.1 Operation of Functions Used 20B The RX62N Group always uses the ETHERC and EDMAC to perform Ethernet communication functions. The ETHERC handles transmit and receive control.
RX62N Group 4.1.2 Ethernet Transmit and Receive Settings Overview of ETHERC Transmitter 32B The ETHERC transmitter assembles transmit data into a frame and outputs it to the MII/RMII when there is a transmit request from the transmit EDMAC. The transmit data is sent to the lines via the MII/RMII by the physical layer transceiver (PHY). Figure 4.2 shows the state transitions of the ETHERC transmitter. • 1. When the transmit enable (ECMR.TE) bit is set to 1, the transmitter enters the transmit idle state.
RX62N Group 4.1.3 Ethernet Transmit and Receive Settings Overview of ETHERC Receiver 3B The ETHERC receiver divides the frame from the MII/RMII into the preamble, SFD, data, and CRC, and the fields from DA (destination address) to the CRC data are output to the receive EDMAC. Figure 4.3 shows the state transitions of the ETHERC receiver. • 1. When the receive enable (ECMR.RE) bit is set to 1, the receiver enters the receive idle state. • 2.
RX62N Group 4.1.4 Ethernet Transmit and Receive Settings Overview of EDMAC 34B The RX62N Group has an on-chip direct memory access controller (EDMAC) that is directly connected to the Ethernet controller (ETHERC). Most buffer management is controlled by the EDMAC by using descriptors. This reduces the load on the CPU, enabling efficient data transmission and reception.
RX62N Group 4.1.5 Ethernet Transmit and Receive Settings Overview of Descriptors 35B To perform a DMA transfer, the EDMAC requires a unit of data called a descriptor that contains information such as the storage address of the transmit or receive data. There are two types of descriptors: transmit descriptors and receive descriptors.
RX62N Group 4.1.7 Ethernet Transmit and Receive Settings Overview of Receive Descriptor 37B Figure 4.6 shows the correspondence between a receive descriptor and a receive buffer. A receive descriptor comprises, beginning from the start of the data, 32-bit units designated RD0, RD1, and RD2, followed by padding. RD0 contains a bit indicating whether the receive descriptor is active or inactive as well as descriptor configuration information and status information.
RX62N Group 4.1.8 Ethernet Transmit and Receive Settings Transmit Descriptor Setting Example 38B Figure 4.7 shows an example in which three transmit descriptor planes and three transmit buffer planes are used (single-frame/single-descriptor). In this case, one frame only is transmitted by a single transmit request. The figure is abbreviated to show only the TD0 portion of each transmit descriptor. The numbers (1), (2), etc., in the figure indicate the execution sequence.
RX62N Group 4.1.9 Ethernet Transmit and Receive Settings Receive Descriptor Setting Example 39B Figure 4.8 shows an example in which three receive descriptor planes and three receive buffer planes are used. Each receive buffer can accommodate 1,536 bytes, and single-frame/single-descriptor operation is used. The figure is abbreviated to show only the RD0 portion of each receive descriptor. The numbers (1), (2), etc., in the figure indicate the execution sequence. Settings are performed as follows. • 1.
RX62N Group 4.1.10 Ethernet Transmit and Receive Settings Function Operating Procedure (Transmission) 40B The EDMAC transmitter is activated when the transmit request (TR) bit in the EDMAC transmit request register (EDTRR) is set to 1 while the value of the TE bit in the ETHERC mode register (ECMR) is 1. After a software reset of the ETHERC and EDMAC, the EDMAC reads the descriptor indicated by the transmit descriptor list start address register (TDLAR).
RX62N Group 4.1.11 Ethernet Transmit and Receive Settings Function Operating Procedure (Reception) 41B The EDMAC receiver is activated when the receive request (RR) bit in the EDMAC receive request register (EDRRR) is set to 1 while the value of the RE bit in ECMR is 1. After a software reset of the ETHERC and EDMAC, the EDMAC reads the descriptor indicated by the receive descriptor list start address register (RDLAR) and, if the RACT bit is set to 1 (active), enters the receive standby state.
RX62N Group 4.1.12 Ethernet Transmit and Receive Settings Function Operating Procedure (Transmission/Reception) 42B The basic settings needed for Ethernet transmission and reception are described below. Figures 4.11 to 4.13 show sample Ethernet transmit/receive setting sequences. Start Reset ETHERC/EDMAC Software reset of ETHERC/EDMAC Write 1 to the SWR bit in the EDMAC mode register (EDMR).
RX62N Group Ethernet Transmit and Receive Settings 1 EDMAC settings • Clear status • Transmit/receive settings • Clear status Write 1 to flag bits in ETHERC/EDMAC status register (EESR) to clear them.
RX62N Group Ethernet Transmit and Receive Settings 2 Set transmit frame in transmit buffer Transmit descriptor settings Update transmit descriptor management pointer Start transmission Set transmit data in the buffer specified by the current descriptor. Set the current descriptor to the transmit-enabled state. Set TFP to a position within the transmit frame. Set TDL to the transmit data length. Set the TACT bit to 1. (This bit is set last.) Set the next descriptor as the current descriptor.
RX62N Group 4.2.3 Ethernet Transmit and Receive Settings Operating Environment of Sample Program 45B Figure 4.14 shows the operating environment of the sample program. For points to be borne in mind with regard to the operating environment, see 4.6.1, Notes on Operating Environment. Figure 4.14 Operating Environment of Sample Program 4.2.
RX62N Group 4.3 Ethernet Transmit and Receive Settings Descriptor Definition in Sample Program 2B The EDMAC does not use the padding area of the descriptor. It can be used freely by the user. The sample program uses this area to specify the start address of the next descriptor, creating a linked structure in software. Figure 4.17 shows the transmit and receive descriptors, and the buffers, used by the sample program.
RX62N Group Ethernet Transmit and Receive Settings struct Descriptor { __evenaccess uint32_t #if __LIT __evenaccess uint16_t __evenaccess uint16_t #else __evenaccess uint16_t __evenaccess uint16_t #endif int8_t struct Descriptor }; status; size; bufsize; bufsize; size; *buf_p; *next; It is possible to change the number of descriptors and the buffer size by changing the macros below, which are defined in r_ether.h.
RX62N Group 4.4 Ethernet Transmit and Receive Settings Ethernet Driver API 23B The functions below are provided as TCP/IP stack driver interfaces. They compose the standard Renesas API (RAPI) for Renesas Ethernet devices. • • • • • R_Ether_Open R_Ether_Close R_Ether_Read R_Ether_Write R_Ether_Write_Sync 4.4.1 R_Ether_Open 47B The R_Ether_Open function initializes the ETHERC, EDMAC, physical layer transceiver (PHY), and transmit/receive data buffers.
RX62N Group 4.4.2 Ethernet Transmit and Receive Settings R_Ether_Close 48B The R_Ether_Close function disables the transmit and receive functions of the ETHERC. This function does not power-down the ETHERC and EDMAC. • Prototype int32_t R_Ether_Close(uint32_t ch); • Arguments ⎯ ch ETHERC channel number specification • Return values R_ETHER_OK(0): Normal completion R_ETHER_ERROR(-1): Error • Properties Declared in r_ether.h file Defined in r_ether.
RX62N Group 4.4.4 Ethernet Transmit and Receive Settings R_Ether_Write 50B The R_Ether_Write function transmits data from the application’s transmit buffer. • Prototype int32_t R_Ether_Write(uint32_t ch, void *buf, uint32_t len); • Arguments ⎯ ch ETHERC channel number specification ⎯ *buf Pointer to Ethernet data to be transmitted ⎯ len Ethernet frame length • Return values R_ETHER_OK(0): Normal completion R_ETHER_ERROR(-1): Error • Properties Declared in r_ether.h file Defined in r_ether.
RX62N Group Ethernet Transmit and Receive Settings Note: Do not use this function because it is not supported by the RX62N Ethernet driver. Use the R_Ether_Write function to transmit data from the transmit buffer. 4.5 Processing Procedure of Sample Program 24B Figures 4.18 and 4.19 show the processing sequence of the sample program, which uses the Ethernet driver API, and figures 4.20 to 4.28 show the processing sequence of the Ethernet driver API and its subordinate functions.
RX62N Group Ethernet Transmit and Receive Settings Sample transmit program SampleEthernetTransmission Sample receive program SampleEthernetReception Start Start R_Ether_Open R_Ether_Open No No Success? Success? Yes Yes R_Ether_Write R_Ether_Read No No Success? Success? Yes Yes No 10 frames transmitted? Yes No 10 frames received? Yes R_Ether_Close No Transmission complete? (TR = 0 in EDTRR?) End Yes R_Ether_Close End Figure 4.
RX62N Group Ethernet Transmit and Receive Settings Open function R_Ether_Open Start Transmit/receive descriptor initialization _eth_fifoInit Initial pointer setting for transmit/receive descriptor Reset ETHERC/EDMAC Initialize the transmit descriptor and receive descriptor. Initialization of pointer variable for managing the current descriptor Set the initial value of the start address of the transmit/receive descriptor list.
RX62N Group Ethernet Transmit and Receive Settings 1 EDMAC settings Write 0x47FF0F9F to the ETHERC/EDMAC status register (EESR) to clear the transmit status. Set the start address of the receive descriptor list in the receive descriptor list start address register (RDLAR). Set the start address of the transmit descriptor list in the transmit descriptor list start address register (TDLAR).
RX62N Group Ethernet Transmit and Receive Settings 2 Set the duplex mode (DM) bit in the ETHERC mode register (ECMR) to match the mode supported by the link partner. No Link partner supports full-duplex mode? Yes Set to half-duplex mode ECMR.DM = 0 Set to full-duplex mode ECMR.DM = 1 Link partner supports 100 Mbps? No Yes Set to 100 Mbps ECMR.RTM = 1 Set to 10 Mbps ECMR.
RX62N Group Ethernet Transmit and Receive Settings Data write function R_Ether_Write Start Initialize variable flag The variable flags are used to write to bits TFP1, TFP0, and TACT in receive descriptor 0 (TD0). Set the variable flag to correspond to TACT = 0, TFP1 = 1, and TFP0 = 0. Transmit data write _eth_fifoWrite Write data to the transmit descriptor and transmit buffer. Can entire transmit size be written to buffer? No Yes Set the variable flag to correspond to TFP0 = 1.
RX62N Group Ethernet Transmit and Receive Settings Data read function R_Ether_Read Start Initialize the internal variable for receive size to 0 and for receive loop to on. Internal variable initialization Receive data read _eth_fifoRead Read data from receive buffer. Yes 2 or more receive frames and receive size = 0? Return R_ETHER_OK No Yes No receive data? End No Receive error? No Yes Receive error handling Normal receive processing See other sequences for processing details.
RX62N Group Ethernet Transmit and Receive Settings Normal receive processing Start No RFP1 = 1? Yes Clear the receive size to 0 when the contents of the receive buffer are the start of the frame. Set receive size to 0 No RFP0 = 1? Yes Turn off receive loop Turn off the receive loop if the contents of the receive buffer include the end of the frame. Update receive size Add the size of the read data to the receive size. Clear RFP Clear the receive frame position (RFP).
RX62N Group Ethernet Transmit and Receive Settings descriptor initialization function _eth_fifoInit Start Update pointer to descriptor to be initialized Transmit descriptor? Yes Set transmit data buffer Clear data buffer No Set the buffer address of the relevant descriptor. Set receive data buffer Clear the relevant data buffer to 0. Set buffer size Set the buffer size for a receive descriptor in RFL and the buffer size for a transmit descriptor in the padding area.
RX62N Group Ethernet Transmit and Receive Settings FIFO write function _eth_fifoWrite Start No Descriptor active? Yes Return –1 End Written data exceeds buffer size? Yes No Write data to buffer No Entire data size written? Yes Return size written End Figure 4.27 Sample Program Descriptor Processing Sequence (2) R01AN0629EJ0101 Rev.1.
RX62N Group Ethernet Transmit and Receive Settings FIFO read function _eth_fifoRead Start Yes Descriptor active? No Yes Frame error? No Return –2 Return –1 No Frame complete? Yes End Set descriptor buffer data size to read size Set buffer size to read size No Read size exceeds buffer size? Read data from buffer Yes Subtract buffer size from read size No Entire read size was read? Yes Return read size End Figure 4.28 Sample Program Descriptor Processing Sequence (3) R01AN0629EJ0101 Rev.1.
RX62N Group 4.6 Ethernet Transmit and Receive Settings Notes on Transmit/Receive Settings 25B 4.6.1 Note on Operating Environment 52B The sample program uses the auto-negotiation function to select the communication mode. If the amount of time required for auto-negotiation by the RX62N and the connection partner of the RX62N (the hub in figure 4.14) differs considerably, communication may fail even though auto-negotiation is successful.
RX62N Group 5. Ethernet Transmit and Receive Settings Endian Mode Selection in Sample Program 4B In the compile options of the RX compiler, big endian is defined as the predefined macro __BIG and little endian as __LIT. The sample program uses these macros to absorb the difference due to the endian mode selection. 5.1 Big Endian Mode 26B For big-endian operation, make the following settings, and set the Pin3 of SW4 on the Renesas Starter Kit +(product number: R0K5562N0C000BE) to OFF (MDE=Hi). • 1.
RX62N Group 7. Ethernet Transmit and Receive Settings Allocation of Sections in Sample Program 6B Table 7.1 shows the allocation of sections by the sample program. For details on the compiler, see section 5, Optimizing Linkage Editor Options, and 8.1, Program Structure, in RX Family C/C++ Compiler, Assembler, Optimizing Linkage Editor: Compiler Package User’s Manual. Table 7.1 Address 0x00001000 Device On-chip RAM 0xFFF80000 On-chip ROM 0xFFF80100 0xFFFFFFD0 7.
RX62N Group 9. Ethernet Transmit and Receive Settings Reference Documents 8B • RX62N Group Hardware Manual (The latest version can be downloaded from the Renesas Electronics Web site.) • RX Family Software Manual (The latest version can be downloaded from the Renesas Electronics Web site.) • RX Family Compiler Package User’s Manual (The latest version can be downloaded from the Renesas Electronics Web site.
RX62N Group Ethernet Transmit and Receive Settings Website and Support • Renesas Electronics Website http://www.renesas.com/ HU U • Inquiries http://www.renesas.com/inquiry HU U All trademarks and registered trademarks are the property of their respective owners. R01AN0629EJ0101 Rev.1.
Revision Record Rev. 1.00 1.01 A-1 Date Dec.27.10 Mar.31.11 Page — 1,3,16,17, 31,49,50 Description Summary First edition issued Change target board to the Renesas Starter Kit +(product number: R0K5562N0C000BE).
General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
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