User`s manual

RX62N Group, RX621 Group 4. Library Reference
Remarks
•
This function must be called before configuring clock-dependent modules.
•
This function modifies the BCLK and SDCLK pins for input or output.
•
The maximum output frequency allowed on the BCLK pin is 25 MHz.
Program example
/* RPDL definitions */
#include "r_pdl_cgc.h"
/* RPDL device-specific definitions */
#include "r_pdl_definitions.h"
void func(void)
{
/* Configure operation using a 12.0 MHz input clock */
/* ICLK = 96 MHz, PCLK = 48 MHz, BCLK = 24 MHz */
R_CGC_Set(
12.0E6,
96E6,
48E6,
24E6,
PDL_CGC_BCLK_DIV_1
);
}
R20UT0084EE0112 Rev.1.12 Page 4-6
July. 16, 2014