User`s manual

RX62N Group, RX621 Group 4. Library Reference
4.2.1. Clock Generation Circuit
1) R_CGC_Set
Synopsis
Configure the clock generation circuit.
Prototype
bool R_CGC_Set(
uint32_t data1,
// Input frequency
uint32_t data2,
// System clock frequency
uint32_t data3,
// Peripheral module clock frequency
uint32_t data4,
// External bus clock frequency
uint16_t data5
// Configuration options
);
Description
Set the clock output frequencies and options.
[data1]
The frequency of the main clock oscillator in Hertz.
[data2]
The desired frequency of the System clock (ICLK) in Hertz.
[data3]
The desired frequency of the Peripheral module clock (PCLK) in Hertz.
[data4]
The desired frequency of the External Bus clock (BCLK) in Hertz.
Specify 0 if the value is not important.
[data5]
Configuration options. If multiple selections are required, use "|" to separate each selection.
The default settings are shown in bold.
•
BCLK pin output control
PDL_CGC_BCLK_DIV_1 or
PDL_CGC_BCLK_DIV_2 or
PDL_CGC_BCLK_DISABLE or
PDL_CGC_BCLK_HIGH
Output the external bus clock (BCLK),
BCLK ÷ 2,
leave the pin as an input
or fix the pin high.
•
SDCLK pin output control
PDL_CGC_SDCLK_ENABLE or
PDL_CGC_SDCLK_DISABLE
Output the SDRAM clock (SDCLK),
or leave the SDCLK pin as a port pin.
•
Oscillation Stop Detection control
PDL_CGC_OSC_STOP_ENABLE or
PDL_CGC_OSC_STOP_DISABLE
Enable or disable the oscillation stop detection
function.
•
Sub-clock oscillator control
PDL_CGC_SUB_CLOCK_ENABLE or
PDL_CGC_SUB_CLOCK_DISABLE
Enable or disable the sub-clock oscillator.
Return value
True if all parameters are valid and exclusive; otherwise false.
For RX62N, the following rules shall be checked:
• Main clock oscillator frequency: 8 to 14 MHz.
• f
ICLK
: 8 to 100 MHz
• f
PCLK
: 8 to 50 MHz
• f
BCLK
: 8 to 100 MHz
• f
ICLK
≥ f
PCLK
and f
ICLK
≥ f
BCLK
• f
ICLK
, f
PCLK
and f
BCLK
are achievable: (main clock oscillator x 8) ÷ 1, 2, 4 or 8.
Category
Clock generation circuit
References
None.
R20UT0084EE0112 Rev.1.12 Page 4-5
July. 16, 2014