User`s manual

RX62N Group, RX621 Group 5. Usage Examples
/* Enter deep software standby mode. An internal reset will occur. */
R_LPC_Control(PDL_LPC_MODE_DEEP_SOFTWARE_STANDBY);
/************** In Deep Software-Standby mode ***************/
/********* Exiting Deep Software-Standby mode By NMI ********/
/*********** Out of Deep Software-Standby mode **************/
/* Find out what caused the exit from deep software standby */
R_LPC_GetStatus(
&status_flags
);
#if SELF_REFRESH_SELECT
/* Enable SDCLK */
R_CGC_Control(PDL_CGC_SDCLK_ENABLE);
/* Configure the bus controller */
/* Select pin-B for CS1#~CS7#; enable SDRAM pins; enable error monitoring */
R_BSC_Create(
PDL_BSC_CS1_B|PDL_BSC_CS2_B|PDL_BSC_CS3_B|PDL_BSC_CS4_B | \
PDL_BSC_CS5_B|PDL_BSC_CS6_B|PDL_BSC_CS7_B,
PDL_BSC_SDRAM_PINS_ENABLE | PDL_BSC_SDRAM_DQM1_ENABLE,
(PDL_BSC_ERROR_ILLEGAL_ADDRESS_ENABLE | PDL_BSC_ERROR_TIME_OUT_ENABLE),
BSC_error_handler,
5
);
/* Configure SDRAM area */
R_BSC_SDRAM_CreateArea(
PDL_BSC_SDRAM_WIDTH_32| PDL_BSC_SDRAM_8_BIT_SHIFT,
0x0FFFu, // RFC = 4096 cycles
0x00u, // REFW = 1 cycle
0x00u, // ARFI = 3 cycles
0x02u, // ARFC = 2 times
0x00u, // PRC = 3 cycles
0x02u, // CL = 2 cycles
0x01u, // WR = 2 cycles
0x00u, // RP = 1 cycle
0x00u, // RCD = 1 cycle
0x00u, // RAS = 1 cycle
0x0220u // SDMOD = 0x220u
);
/* Start Auto-Refresh */
R_BSC_Control(PDL_BSC_SDRAM_AUTO_REFRESH_ENABLE);
/* Check the status flags */
do{
R_BSC_GetStatus(&status1, &status2, &sdram_status);
} while(sdram_status != 0);
/* Start Self-Refresh */
R_BSC_Control(PDL_BSC_SDRAM_SELF_REFRESH_ENABLE);
/* to release IO ports */
R_LPC_Control(
PDL_LPC_IO_RELEASE
);
/**************** In Self-Refresh mode **********************/
/* read SDRAM, should fail */
temp = *sdram_location_32;
/**************** Exiting Self-Refresh *********************/
R20UT0084EE0112 Rev.1.12 Page 5-13
July. 16, 2014