User`s manual

RX62N Group, RX621 Group 4. Library Reference
4.2.24. 12-bit Analog to Digital Converter
1) R_ADC_12_Create
Synopsis
Configure the 12-bit ADC unit.
Prototype
bool R_ADC_12_Create(
uint8_t data1,
// Unit selection
uint32_t data2,
// Conversion options
uint16_t data3,
// Trigger selection
uint16_t data4,
// Value addition mode options
void * func,
// Callback function
uint8_t data5
// Interrupt priority level
);
Description (1/2)
Set the ADC mode and operating condition.
[data1]
Select the ADC unit to be configured. This must always be 0.
[data2]
Conversion options. To set multiple options at the same time, use "|" to separate each value.
The default settings are shown in bold.
•
Scan mode
PDL_ADC_12_SCAN_SINGLE or
PDL_ADC_12_SCAN_CONTINUOUS
Select Single scan or
Continuous scan mode.
•
Input channel selection
PDL_ADC_12_CHANNEL_0
Carry out a conversion on each of the selected
channels AN0 to AN7.
PDL_ADC_12_CHANNEL_1
PDL_ADC_12_CHANNEL_2
PDL_ADC_12_CHANNEL_3
PDL_ADC_12_CHANNEL_4
PDL_ADC_12_CHANNEL_5
PDL_ADC_12_CHANNEL_6
PDL_ADC_12_CHANNEL_7
•
Clock division
PDL_ADC_12_DIV_1 or
PDL_ADC_12_DIV_2 or
PDL_ADC_12_DIV_4 or
PDL_ADC_12_DIV_8
Use the peripheral clock, PCLK ÷ 1, 2, 4 or 8.
•
Data alignment
PDL_ADC_12_DATA_ALIGNMENT_LEFT or
PDL_ADC_12_DATA_ALIGNMENT_RIGHT
The alignment of the 12-bit ADC conversion
result within the 16-bit register.
Ignored for channels using value addition
mode (the 14-bit result is always left-aligned).
•
Result register clearing
PDL_ADC_12_RETAIN_RESULT or
PDL_ADC_12_CLEAR_RESULT
Retain or clear the value in each result register after it
has been read.
•
DMAC / DTC trigger control
PDL_ADC_12_DMAC_DTC_TRIGGER_DISABLE or
PDL_ADC_12_DMAC_TRIGGER_ENABLE or
PDL_ADC_12_DTC_TRIGGER_ENABLE
Disable or enable activation of the
DMAC or DTC when a scan cycle
completes.
R20UT0084EE0112 Rev.1.12 Page 4-215
July. 16, 2014