User`s manual
RX62N Group, RX621 Group 4. Library Reference
Description (2/3)
[data3]
Configure the data format. If multiple selections are required, use "|" to separate each selection.
The default settings are shown in bold.
•
Buffer size
PDL_SPI_BUFFER_64 or
PDL_SPI_BUFFER_128
Select a buffer size of 64 bits (up to four 16-bit frames) or
128 bits (up to four 32-bit frames).
•
Frame configuration selection (refer to figure 32.2 in the hardware manual).
Selection
Number of
command
transfers
Number of frames in
each command transfer
Total number of
transfer frames
PDL_SPI_FRAME_1_1 or
PDL_SPI_FRAME_1_2 or
PDL_SPI_FRAME_1_3 or
PDL_SPI_FRAME_1_4 or
PDL_SPI_FRAME_2_1 or
PDL_SPI_FRAME_2_2 or
PDL_SPI_FRAME_3 or
PDL_SPI_FRAME_4 or
PDL_SPI_FRAME_5 or
PDL_SPI_FRAME_6 or
PDL_SPI_FRAME_7 or
PDL_SPI_FRAME_8
1
1
1
1
2
2
3
4
5
6
7
8
1
2
3
4
1
2
1
1
1
1
1
1
1
2
3
4
2
4
3
4
5
6
7
8
•
Parity bit control
PDL_SPI_PARITY_NONE or
PDL_SPI_PARITY_EVEN or
PDL_SPI_PARITY_ODD
Disable or enable the addition of the parity bit.
[data4]
Extended timing control (optional).
All items apply only to Master mode.
If multiple selections are required, use "|" to separate each selection.
The default settings are shown in bold. Specify PDL_NO_DATA if not required.
•
Extended clock delay
PDL_SPI_CLOCK_DELAY_1 or
PDL_SPI_CLOCK_DELAY_2 or
PDL_SPI_CLOCK_DELAY_3 or
PDL_SPI_CLOCK_DELAY_4 or
PDL_SPI_CLOCK_DELAY_5 or
PDL_SPI_CLOCK_DELAY_6 or
PDL_SPI_CLOCK_DELAY_7 or
PDL_SPI_CLOCK_DELAY_8
The number of bit clock periods between the assertion of
the SSL pin and the start of RSPCK oscillation.
Ignored in Slave mode.
•
Extended SSL negation delay
PDL_SPI_SSL_DELAY_1 or
PDL_SPI_SSL_DELAY_2 or
PDL_SPI_SSL_DELAY_3 or
PDL_SPI_SSL_DELAY_4 or
PDL_SPI_SSL_DELAY_5 or
PDL_SPI_SSL_DELAY_6 or
PDL_SPI_SSL_DELAY_7 or
PDL_SPI_SSL_DELAY_8
The number of bit clock periods between the end of RSPCK
oscillation and the negation of the active SSL pin.
Ignored in Slave mode.
•
Extended next-access delay
PDL_SPI_NEXT_DELAY_1 or
PDL_SPI_NEXT_DELAY_2 or
PDL_SPI_NEXT_DELAY_3 or
PDL_SPI_NEXT_DELAY_4 or
PDL_SPI_NEXT_DELAY_5 or
PDL_SPI_NEXT_DELAY_6 or
PDL_SPI_NEXT_DELAY_7 or
PDL_SPI_NEXT_DELAY_8
The number of bit clock periods (plus two cycles of the
peripheral clock) between the end of one frame and the
start of the next frame.
Ignored in Slave mode.
R20UT0084EE0112 Rev.1.12 Page 4-205
July. 16, 2014