User`s manual

RX62N Group, RX621 Group 4. Library Reference
4.2.23. Serial Peripheral Interface
1) R_SPI_Create
Synopsis
Configure an SPI channel.
Prototype
bool R_SPI_Create(
uint8_t data1,
// Channel selection
uint32_t data2,
// Channel configuration
uint32_t data3,
// Data format
uint32_t data4,
// Extended timing control
uint32_t data5
// Bit rate or register value
);
Description (1/3)
Set up the selected SPI channel.
[data1]
Select channel SPIn (where n = 0 to 1).
[data2]
Configure the channel mode and connection settings.
If multiple selections are required, use "|" to separate each selection.
The default settings are shown in bold.
•
Connection mode
PDL_SPI_MODE_SPI_MASTER or
PDL_SPI_MODE_SPI_MULTI_MASTER or
PDL_SPI_MODE_SPI_SLAVE or
PDL_SPI_MODE_SYNC_MASTER or
PDL_SPI_MODE_SYNC_SLAVE
The required SPI (four-wire) or Clock
synchronous (three-wire operation) connection
type.
•
Reception control
PDL_SPI_FULL_DUPLEX or
PDL_SPI_TRANSMIT_ONLY
Enable or disable reception operations.
•
Pin selection and control
PDL_SPI_PIN_CMOS or
PDL_SPI_PIN_OPEN_DRAIN
Select CMOS or Open-drain output type.
PDL_SPI_PIN_A or
PDL_SPI_PIN_B
Select the -A or -B pins for signals MISO, MOSI,
RSPCK, SSL0, SSL1, SSL2 and SSL3.
PDL_SPI_PIN_RSPCK_ENABLE or
PDL_SPI_PIN_RSPCK_DISABLE
Enable or disable signal RSPCK.
PDL_SPI_PIN_MOSI_ENABLE or
PDL_SPI_PIN_MOSI_DISABLE
Enable or disable output signal MOSI.
PDL_SPI_PIN_MISO_ENABLE or
PDL_SPI_PIN_MISO_DISABLE
Enable or disable input signal MISO.
PDL_SPI_PIN_SSL0_LOW or
PDL_SPI_PIN_SSL0_HIGH or
PDL_SPI_PIN_SSL0_DISABLE
Select active-low,
active-high or
disabled for output signal SSL0.
PDL_SPI_PIN_SSL1_LOW or
PDL_SPI_PIN_SSL1_HIGH or
PDL_SPI_PIN_SSL1_DISABLE
Select active-low,
active-high or
disabled for output signal SSL1.
PDL_SPI_PIN_SSL2_LOW or
PDL_SPI_PIN_SSL2_HIGH or
PDL_SPI_PIN_SSL2_DISABLE
Select active-low,
active-high or
disabled for output signal SSL2.
PDL_SPI_PIN_SSL3_LOW or
PDL_SPI_PIN_SSL3_HIGH or
PDL_SPI_PIN_SSL3_DISABLE
Select active-low,
active-high or
disabled for output signal SSL3.
PDL_SPI_PIN_MOSI_IDLE_LAST or
PDL_SPI_PIN_MOSI_IDLE_LOW or
PDL_SPI_PIN_MOSI_IDLE_HIGH
The MOSI output state when no SSLn pin is
active.
R20UT0084EE0112 Rev.1.12 Page 4-204
July. 16, 2014