User`s manual

RX62N Group, RX621 Group 4. Library Reference
Description (3/3)
[data3]
Select the SCI transfer rate.
See the Remarks section for the maximum rate that the device can support.
The format may be either:
•
The transfer bit rate in bits per second (bps).
The clock division values will be calculated using this value.
This format is valid only when the on-chip baud rate generator is selected as the data clock
source (in parameter data2).
Or the following, using "|" to separate each selection.
•
b31
b30 – b24
b23 – b0
1 0
A value between 256 (0x100) and 16,776,960 (0xFFFF00) that is nearest
to the transfer bit rate.
•
ABCS selection (required for asynchronous mode)
PDL_SCI_CYCLE_BIT_16 or
PDL_SCI_CYCLE_BIT_8
Select 16 or 8 base clock cycles for one bit period.
•
CKS selection (required if the on-chip baud rate generator is selected as the data clock source)
PDL_SCI_PCLK_DIV_1 or
PDL_SCI_PCLK_DIV_4 or
PDL_SCI_PCLK_DIV_16 or
PDL_SCI_PCLK_DIV_64
Select the internal clock signal PCLK ÷ 1, 4, 16 or 64 as the
baud rate generator clock source.
•
BRR setting (required if the on-chip baud rate generator is selected as the data clock source)
The BRR register value, between 0 and 255.
[data4]
The interrupt priority level. Select between 1 (lowest priority) and 15 (highest priority).
This parameter will be ignored if PDL_NO_FUNC is specified for parameter func in functions
R_SCI_Send or R_SCI_Receive.
Return value
True if all parameters are valid, exclusive and achievable; otherwise false.
Category
SCI
Reference
R_CGC_Set, R_SCI_Set, R_SCI_Send, R_SCI_Receive
Remarks
•
Function R_CGC_Set must be called before any use of this function.
•
This function configures each SCI pin that is required for operation. User needs to ensure no
higher priority modules using the same pins as required by SCI.
•
The wait time of 1 data bit period that is required during configuration is handled within this
function.
•
The range of achievable bit rates is listed below.
Mode
Data
clock
source
Limit
f
PCLK
50 MHz 48 MHz 32 MHz 12.5 MHz 12 MHz 8 MHz
Asynchro-
nous
Internal
Minimum
96
92
62
24
23
16
Maximum
3,125,000
3,000,000
2,000,000
781,250
750,000
500,000
External
1,562,500
1,500,000
1,000,000
390,625
375,000
250,000
Synchro-
nous
Internal
Minimum
763
733
489
191
184
123
Maximum
6,250,000
6,000,000
4,000,000
1,562,500
1,500,000
1,000,000
External
8,333,333
8,000,000
5,333,333
2,083,333
2,000,000
1,333,333
Smart card Internal
Minimum
3
3
2
1
1
1
Maximum
781,250
750,000
500,000
195,312
187,500
125,000
R20UT0084EE0112 Rev.1.12 Page 4-172
July. 16, 2014