User`s manual

RX62N Group, RX621 Group 4. Library Reference
Description (2/3)
Options which are available in Clock Synchronous mode
•
Data clock source selection
PDL_SCI_CLK_INT_OUT or
Select the On-chip baud rate generator.
The SCKn pin outputs the bit clock.
PDL_SCI_CLK_EXT
Input the clock to the SCKn pin.
Options which are available in Smart Card Interface mode
•
Data inversion
PDL_SCI_INVERSION_OFF or
PDL_SCI_INVERSION_ON
Control data inversion (transmission and reception).
•
Base clock pulse cycle count
PDL_SCI_BCP_32 or
PDL_SCI_BCP_64 or
PDL_SCI_BCP_93 or
PDL_SCI_BCP_128 or
PDL_SCI_BCP_186 or
PDL_SCI_BCP_256 or
PDL_SCI_BCP_372 or
PDL_SCI_BCP_512
The number of base clock cycles in a 1-bit data transfer
period.
•
Parity selection
PDL_SCI_PARITY_EVEN or
PDL_SCI_PARITY_ODD
Select even or odd parity bit.
•
Block transfer mode selection
PDL_SCI_BLOCK_MODE_OFF or
PDL_SCI_BLOCK_MODE_ON
Control Block transfer mode.
•
GSM mode selection
PDL_SCI_GSM_MODE_OFF or
PDL_SCI_GSM_MODE_ON
Control GSM mode.
•
SCKn pin output control
Normal mode
GSM mode
PDL_SCI_SCK_OUTPUT_OFF or
I/O pin
Not applicable
PDL_SCI_SCK_OUTPUT_LOW or
Not applicable.
Fixed low.
PDL_SCI_SCK_OUTPUT_ON or
Outputs the bit clock.
PDL_SCI_SCK_OUTPUT_HIGH
Not applicable
Fixed high.
R20UT0084EE0112 Rev.1.12 Page 4-171
July. 16, 2014