User`s manual

RX62N Group, RX621 Group 4. Library Reference
Description (2/2)
[data3]
Interrupt control.
If multiple selections are required, use "|" to separate each selection.
All settings are optional. Specify PDL_NO_DATA if no control is required.
•
High impedance request response
PDL_POE_IRQ_HI_Z_0_3_DISABLE
Control interrupts on detection of any high
impedance request on pins POE0 to POE3.
PDL_POE_IRQ_HI_Z_0_3_ENABLE
PDL_POE_IRQ_HI_Z_4_7_DISABLE
Control interrupts on detection of any high
impedance request on pins POE4 to POE7.
PDL_POE_IRQ_HI_Z_4_7_ENABLE
PDL_POE_IRQ_HI_Z_8_DISABLE
Control interrupts on detection of a high impedance
request on pin POE8.
PDL_POE_IRQ_HI_Z_8_ENABLE
PDL_POE_IRQ_HI_Z_9_DISABLE
Control interrupts on detection of a high impedance
request on pin POE9.
PDL_POE_IRQ_HI_Z_9_ENABLE
•
Output short detection response
PDL_POE_IRQ_SHORT_3_4_DISABLE
Control interrupts on detection of a short on any
MTU channel 3 or 4 two-phase output pair.
PDL_POE_IRQ_SHORT_3_4_ENABLE
PDL_POE_IRQ_SHORT_9_10_DISABLE
Control interrupts on detection of a short on any
MTU channel 9 or 10 two-phase output pair.
PDL_POE_IRQ_SHORT_9_10_ENABLE
Return value
True if all parameters are valid and exclusive; otherwise false.
Category
Port Output Enable
Reference
R_POE_Create
Remarks
•
Call R_POE_Create before using this function.
•
Clearing a level-triggered event flag will fail if the trigger is still asserted.
•
Interrupt disabling is processed at the start of the function and enabling is processed at the
end. This allows a flag to be cleared and the interrupt re-enabled in one function call.
•
Do not clear an Output Short Flag ( using PDL_POE_FLAG_SHORT_x_x_CLEAR ) until the
pins, that simultaneously became active, have been set to the inactive level. Inactive-level
outputs can be achieved by setting the MTU, GPT, and ALR1 internal registers.
Program example
/* RPDL definitions */
#include "r_pdl_poe.h"
/* RPDL device-specific definitions */
#include "r_pdl_definitions.h"
void func(void)
{
/* Select high impedance on the MTU6 I/O pins */
R_POE_Control(
PDL_POE_MTU6_HI_Z_ON,
PDL_NO_DATA,
PDL_NO_DATA
);
}
R20UT0084EE0112 Rev.1.12 Page 4-119
July. 16, 2014