User`s manual

RX62N Group, RX621 Group 4. Library Reference
Description (5/8)
[data6]
Configure the operation for general registers TGRA and TGRB. Valid for n = 0 to 4 or 6 to 10.
If multiple selections are required, use "|" to separate each selection.
The default settings are shown in bold. Specify PDL_NO_DATA to use the defaults.
•
Input capture / output compare control for register TGRA
PDL_MTU2_A_OC_DISABLED or
PDL_MTU2_A_OC_LOW or
PDL_MTU2_A_OC_LOW_CM_HIGH or
PDL_MTU2_A_OC_LOW_CM_INV or
PDL_MTU2_A_OC_HIGH_CM_LOW or
PDL_MTU2_A_OC_HIGH or
PDL_MTU2_A_OC_HIGH_CM_INV or
MTIOCnA output disabled.
MTIOCnA output low.
MTIOCnA initial output low; goes high at compare
match.
MTIOCnA initial output low; toggles at compare
match.
MTIOCnA initial output high; goes low at compare
match.
MTIOCnA output high.
MTIOCnA initial output high; toggles at compare
match.
PDL_MTU2_A_IC_RISING_EDGE or
PDL_MTU2_A_IC_FALLING_EDGE or
PDL_MTU2_A_IC_BOTH_EDGES or
Input capture at MTIOCnA rising edge.
Input capture at MTIOCnA falling edge.
Input capture at MTIOCnA both edges.
PDL_MTU2_A_IC_COUNT or
Input capture at channel (n+1) up-count or
down-count. Valid only for n = 0 or 6.
PDL_MTU2_A_IC_CM_IC
Input capture at channel (n-1) TGRC compare match
or input capture. Valid only for n = 1 or 7.
•
Input capture / output compare control for register TGRB.
PDL_MTU2_B_OC_DISABLED or
PDL_MTU2_B_OC_LOW or
PDL_MTU2_B_OC_LOW_CM_HIGH or
PDL_MTU2_B_OC_LOW_CM_INV or
PDL_MTU2_B_OC_HIGH_CM_LOW or
PDL_MTU2_B_OC_HIGH or
PDL_MTU2_B_OC_HIGH_CM_INV or
MTIOCnB output disabled.
MTIOCnB output low.
MTIOCnB initial output low; goes high at compare
match.
MTIOCnB initial output low; toggles at compare
match.
MTIOCnB initial output high; goes low at compare
match.
MTIOCnB output high.
MTIOCnB initial output high; toggles at compare
match.
PDL_MTU2_B_IC_RISING_EDGE or
PDL_MTU2_B_IC_FALLING_EDGE or
PDL_MTU2_B_IC_BOTH_EDGES or
Input capture at MTIOCnB rising edge.
Input capture at MTIOCnB falling edge.
Input capture at MTIOCnB both edges.
PDL_MTU2_B_IC_COUNT or
Input capture at channel (n+1) up-count or
down-count. Valid only for n = 0 or 6.
PDL_MTU2_B_IC_CM_IC
Input capture at channel (n-1) TGRC compare match
or input capture. Valid only for n = 1 or 7.
•
Cascade input capture control. Valid in cascade mode for n = 1 or 7.
Channel n forms the higher 16 bits and channel (n+1) forms the lower 16 bits.
PDL_MTU2_CASCADE_AL_IC_EXC_H or
PDL_MTU2_CASCADE_AL_IC_INC_H
Exclude or include pin MTIOCnA in the TGRA
input capture conditions for channel (n+1).
PDL_MTU2_CASCADE_BL_IC_EXC_H or
PDL_MTU2_CASCADE_BL_IC_INC_H
Exclude or include pin MTIOCnB in the TGRB
input capture conditions for channel (n+1).
PDL_MTU2_CASCADE_AH_IC_EXC_L or
PDL_MTU2_CASCADE_AH_IC_INC_L
Exclude or include pin MTIOC(n+1)A in the
TGRA input capture conditions for channel n.
PDL_MTU2_CASCADE_BH_IC_EXC_L or
PDL_MTU2_CASCADE_BH_IC_INC_L
Exclude or include pin MTIOC(n+1)B in the
TGRB input capture conditions for channel n.
R20UT0084EE0112 Rev.1.12 Page 4-96
July. 16, 2014