User`s manual

RX62N Group, RX621 Group 4. Library Reference
Description (2/8)
•
Synchronous mode. Valid for n = 0 to 4 or 6 to 10.
PDL_MTU2_SYNC_DISABLE or
PDL_MTU2_SYNC_ENABLE
Disable or enable synchronous presetting / clearing.
•
DMAC / DTC event trigger control. Valid for n = 0 to 4 or 6 to 10 unless stated otherwise.
PDL_MTU2_TGRA_DMAC_DTC_TRIGGER_DISABLE or
PDL_MTU2_TGRA_DMAC_TRIGGER_ENABLE or
PDL_MTU2_TGRA_DTC_TRIGGER_ENABLE
TGRA compare match or input
capture.
PDL_MTU2_TGRB_DTC_TRIGGER_DISABLE or
PDL_MTU2_TGRB_DTC_TRIGGER_ENABLE
TGRB compare match or input capture.
PDL_MTU2_TGRC_DTC_TRIGGER_DISABLE or
PDL_MTU2_TGRC_DTC_TRIGGER_ENABLE
TGRC compare match or input capture.
Valid for n = 0, 3, 4, 6, 9 and 10.
PDL_MTU2_TGRD_DTC_TRIGGER_DISABLE or
PDL_MTU2_TGRD_DTC_TRIGGER_ENABLE
TGRD compare match or input capture.
Valid for n = 0, 3, 4, 6, 9 and 10.
PDL_MTU2_TCIV_DTC_TRIGGER_DISABLE or
PDL_MTU2_TCIV_DTC_TRIGGER_ENABLE
Counter overflow or underflow.
Valid for n = 4 or 10.
•
DTC event trigger control. Valid for n = 5 or 11.
PDL_MTU2_TGRU_DTC_TRIGGER_DISABLE or
PDL_MTU2_TGRU_DTC_TRIGGER_ENABLE
TGRU compare match or input capture.
PDL_MTU2_TGRV_DTC_TRIGGER_DISABLE or
PDL_MTU2_TGRV_DTC_TRIGGER_ENABLE
TGRV compare match or input capture.
PDL_MTU2_TGRW_DTC_TRIGGER_DISABLE or
PDL_MTU2_TGRW_DTC_TRIGGER_ENABLE
TGRW compare match or input capture.
[data3]
Configure the counter operation.
If multiple selections are required, use "|" to separate each selection.
The default settings are shown in bold. Specify PDL_NO_DATA to use the defaults.
•
TCNT counter clock source selection. Valid for n = 0 to 4 or 6 to 10 unless stated otherwise.
PDL_MTU2_CLK_PCLK_DIV_1 or
PDL_MTU2_CLK_PCLK_DIV_4 or
PDL_MTU2_CLK_PCLK_DIV_16 or
PDL_MTU2_CLK_PCLK_DIV_64 or
The internal clock signal PCLK ÷ 1, 4, 16 or 64.
PDL_MTU2_CLK_PCLK_DIV_256 or
PCLK ÷ 256. Valid for n = 1, 3, 4, 7, 9 and 10.
PDL_MTU2_CLK_PCLK_DIV_1024 or
PCLK ÷ 1024. Valid for n = 2, 3, 4, 8, 9 and 10.
PDL_MTU2_CLK_MTCLKA or
MTCLKA pin input. Valid for n = 0 to 4.
PDL_MTU2_CLK_MTCLKB or
MTCLKB pin input. Valid for n = 0 to 4.
PDL_MTU2_CLK_MTCLKC or
MTCLKC pin input. Valid for n = 0 or 2.
PDL_MTU2_CLK_MTCLKD or
MTCLKD pin input. Valid for n = 0.
PDL_MTU2_CLK_MTCLKE or
MTCLKE pin input. Valid for n = 6 to 10.
PDL_MTU2_CLK_MTCLKF or
MTCLKF pin input. Valid for n = 6 to 10.
PDL_MTU2_CLK_MTCLKG or
MTCLKG pin input. Valid for n = 6 or 8.
PDL_MTU2_CLK_MTCLKH or
MTCLKH pin input. Valid for n = 6.
PDL_MTU2_CLK_CASCADE
The overflow / underflow signal from channel (n+1).
Valid for n = 1 or 7.
•
TCNT counter clock edge selection. Valid for n = 0 to 4 or 6 to 10.
PDL_MTU2_CLK_RISING or
PDL_MTU2_CLK_FALLING or
PDL_MTU2_CLK_BOTH
The TCNT counter clock signal shall be counted on
rising, falling or both edges.
•
TCNT counter clearing. Valid for n = 0 to 4 or 6 to 10 unless stated otherwise.
PDL_MTU2_CLEAR_DISABLE or
Clearing is disabled.
PDL_MTU2_CLEAR_TGRA or
Cleared by TGRA compare match or input capture.
PDL_MTU2_CLEAR_TGRB or
Cleared by TGRB compare match or input capture.
PDL_MTU2_CLEAR_SYNC
Cleared by counter clearing on another channel
configured for synchronous operation.
PDL_MTU2_CLEAR_TGRC or
Cleared by TGRC compare match or input capture.
Valid for n = 0, 3, 4, 6, 9 and 10.
PDL_MTU2_CLEAR_TGRD or
Cleared by TGRD compare match or input capture.
Valid for n = 0, 3, 4, 6, 9 and 10.
R20UT0084EE0112 Rev.1.12 Page 4-93
July. 16, 2014