User`s manual

RX62N Group, RX621 Group 4. Library Reference
Description (2/2)
[data7]
The value to be set to CL bits in SDRAM Timing Register (SDTR). Valid between 0x01 and 0x03.
Setting of 0x00 or more than 0x03 is prohibited.
[data8]
The value to be set to WR bit in SDRAM Timing Register (SDTR). Valid between 0x00 and 0x01.
[data9]
The value to be set to RP bits in SDRAM Timing Register (SDTR). Valid between 0x00 and 0x07.
[data10]
The value to be set to RCD bits in SDRAM Timing Register (SDTR). Valid between 0x00 and 0x03.
[data11]
The value to be set to RAS bits in SDRAM Timing Register (SDTR). Valid between 0x00 and 0x06.
[data12]
The value to be written to the SDRAM mode register. Only the lower 15 bits are valid. Please refer
to hardware manual for restriction on SDRAM mode setting.
Return value
True if all parameters are valid and exclusive; otherwise false.
Category
Bus Controller
Reference
R_BSC_Create
Remarks
•
Ensure that function R_BSC_Create is called once before using this function.
•
The endian mode of the CPU is selected by the MDE pin (low = little endian; high = big endian).
•
Port Function Control register PF5BUS is modified by this function.
•
The cycle count parameters are not checked for validity. Use the hardware manual to check
these values.
•
The exact values in parameters, data2 to data11, are to be set to respective bit-field in SDRAM
registers. For the corresponding cycle / count value, please refer to the hardware manual.
•
There is no SDRAM area for the 100-pin and 85-pin packages.
Program example
/* RPDL definitions */
#include "r_pdl_bsc.h"
/* RPDL device-specific definitions */
#include "r_pdl_definitions.h"
void func(void)
{
/* Configure SDRAM: 8-bit width, 10-bit address shift */
R_BSC_SDRAM_CreateArea(
PDL_BSC_SDRAM_WIDTH_32| PDL_BSC_SDRAM_8_BIT_SHIFT,
0x0FFFu,
0x00u,
0x00u,
0x02u,
0x00u,
0x02u,
0x01u,
0x00u,
0x00u,
0x00u,
0x0220u
);
}
R20UT0084EE0112 Rev.1.12 Page 4-58
July. 16, 2014