User`s manual

RX62N Group, RX621 Group 4. Library Reference
3) R_BSC_SDRAM_CreateArea
Synopsis
Configure the SDRAM area.
Prototype
bool R_BSC_SDRAM_CreateArea(
uint16_t data1,
// Configuration selection
uint16_t data2,
// RFC cycles
uint8_t data3,
// REFW cycles
uint8_t data4,
// ARFI cycles
uint8_t data5,
// ARFC count
uint8_t data6,
// PRC cycles
uint8_t data7,
// CL cycles
uint8_t data8,
// WR cycles
uint8_t data9,
// RP cycles
uint8_t data10,
// RCD cycles
uint8_t data11,
// RAS cycles
uint16_t data12
// SDRAM mode
);
Description (1/2)
Set up the SDRAM area.
[data1]
Configure the operation of SDRAM area.
If multiple selections are required, use "|" to separate each selection.
The default settings are shown in bold. Specify PDL_NO_DATA to use the defaults.
•
SDRAM bus width
PDL_BSC_SDRAM_WIDTH_16 or
PDL_BSC_SDRAM_WIDTH_8 or
PDL_BSC_SDRAM_WIDTH_32
Select 16-bit, 8-bit or 32-bit data bus width
•
Endian mode
PDL_BSC_SDRAM_ENDIAN_SAME or
PDL_BSC_SDRAM_ENDIAN_OPPOSITE
Set the bus endian mode to be the same or
opposite to that of the CPU.
•
Continuous access mode
PDL_BSC_SDRAM_CONT_ACCESS_DISABLE or
PDL_BSC_SDRAM_CONT_ACCESS_ENABLE
Disable or enable Continuous Access.
•
Address multiplex selection
PDL_BSC_SDRAM_8_BIT_SHIFT or
PDL_BSC_SDRAM_9_BIT_SHIFT or
PDL_BSC_SDRAM_10_BIT_SHIFT or
PDL_BSC_SDRAM_11_BIT_SHIFT
Select the size of shift in address multiplexing:
8-bit shift, 9-bit shift, 10-bit shift, or 11-bit shift.
[data2]
The value to be set to RFC bits in SDRAM Refresh Control Register (SDRFCR). Valid between
0x0001 and 0x0FFF. Setting of 0x0000 is prohibited.
[data3]
The value to be set to REFW bits in SDRAM Refresh Control Register (SDRFCR). Valid between
0x00 and 0x0F.
[data4]
The value to be set to ARFI bits in SDRAM Initialization Register (SDIR). Valid between 0x00 and
0x0F.
[data5]
The value to be set to ARFC bits in SDRAM Initialization Register (SDIR). Valid between 0x01 and
0x0F. Setting of 0x00 is prohibited.
[data6]
The value to be set to PRC bits in SDRAM Initialization Register (SDIR). Valid between 0x00 and
0x07.
R20UT0084EE0112 Rev.1.12 Page 4-57
July. 16, 2014