User`s manual

RX62N Group, RX621 Group 4. Library Reference
4.2.8. Bus Controller
1) R_BSC_Create
Synopsis
Configure the external bus controller.
Prototype
bool R_BSC_Create(
uint32_t data1,
// Configuration1 (pin select control)
uint32_t data2,
// Configuration2 (output enable control)
uint8_t data3,
// Configuration3 (error control)
void * func,
// Callback function
uint8_t data4
// Interrupt priority level
);
Description (1/2)
Configure the I/O pins, error detection and register the callback function
Control the external bus controller.
If multiple selections are required, use "|" to separate each selection.
The default settings are shown in bold. Specify PDL_NO_DATA to use the defaults.
[data1]
•
Chip select pin selection (only required for each external memory area that is enabled).
PDL_BSC_CS0_A or
PDL_BSC_CS0_B
Select pin CS0#-A or CS0#-B.
PDL_BSC_CS1_A or
PDL_BSC_CS1_B or
PDL_BSC_CS1_C
Select pin CS1#-A, CS1#-B or CS1#-C.
PDL_BSC_CS2_A or
PDL_BSC_CS2_B or
PDL_BSC_CS2_C
Select pin CS2#-A, CS2#-B or CS2#-C.
PDL_BSC_CS3_A or
PDL_BSC_CS3_B or
PDL_BSC_CS3_C
Select pin CS3#-A, CS3#-B or CS3#-C.
PDL_BSC_CS4_A or
PDL_BSC_CS4_B or
PDL_BSC_CS4_C
Select pin CS4#-A, CS4#-B or CS4#-C.
PDL_BSC_CS5_A or
PDL_BSC_CS5_B or
PDL_BSC_CS5_C
Select pin CS5#-A, CS5#-B or CS5#-C.
PDL_BSC_CS6_A or
PDL_BSC_CS6_B or
PDL_BSC_CS6_C
Select pin CS6#-A, CS6#-B or CS6#-C.
PDL_BSC_CS7_A or
PDL_BSC_CS7_B or
PDL_BSC_CS7_C
Select pin CS7#-A, CS7#-B or CS7#-C.
•
Address (A23-A16) pin selection
PDL_BSC_A23_A16_A or
PDL_BSC_A23_A16_B
Select pins A23-A to A16-A, or A23-B to A16-B.
•
WAIT pin selection.
PDL_BSC_WAIT_NOT_USED or
The WAIT signal is not used.
PDL_BSC_WAIT_A or
PDL_BSC_WAIT_B or
PDL_BSC_WAIT_C or
PDL_BSC_WAIT_D
If the WAIT signal is used and the package supports
alternative WAIT pins, select the appropriate pin WAIT#-A,
WAIT#-B, WAIT#-C or WAIT#-D.
R20UT0084EE0112 Rev.1.12 Page 4-51
July. 16, 2014