User's Manual

Rev. 5.00, 09/03, page 687 of 760
CKIO
A12 or A10
RD/WR
CSn
RAS
CAS
BS
DQMxx
CKE
A25 to A16
A15 to A0
Tr
Tc1 Tc2 Tc3 Tc4 (Trwl) (Tpc) (Tpc)
(High)
D31 to D0
tAD
Row address
Row
address
Write A
command
Write command
Row
address
tAD tAD
tAD tAD
tCSD3
tRWD tRWD
tAD
tAD tAD
tAD
tCSD3
tRWD
tRASD2 tRASD2
tDQMD
tWDD2
tWDD2
tBSD
tCASD2
tDQMD
tWDH2
tBSD
tCASD2
Column address (1-4)
t
DAKD1
t
DAKD1
DACKn
Figure 23.28 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write ×
××
× 4),
RCD =
==
= 0, TPC =
==
= 1, TRWL = 0)