User's Manual

ManualsBrandsRenesas ManualsStereo SystemRenesas Renesas Stereo System SH7709S

2003.9.18

SH7709S

Group

Hardware Manual

Renesas 32-Bit RISC Microcomputer

SuperH RISC engine Family/SH7700 Series

Rev.5.00

The revision list can be viewed directly by

clicking the title page.

The revision list summarizes the locations of

revisions and additions. Details should always

be checked by referring to the relevant text.

Summary of content (807 pages)

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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7709S Group 32 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series Rev.5.00 2003.9.
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Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series SH7709S Group Hardware Manual REJ09B0081-0500O
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • • CPU and System-Control Modules On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
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Preface This LSI is a microprocessor with the 32-bit SH-3 CPU as its core and peripheral functions necessary for configuring a user system. This LSI is built in with a variety of peripheral functions such as cache memory, memory management unit (MMU), interrupt controller, timer, three serial communication interfaces, realtime clock (RTC), use break controller (UBC), bus state controller (BSC) and I/O ports.
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• User manuals for development tools Name of Document Document No. C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual ADE-702-246 Simulator/Debugger User’s Manual ADE-702-186 Embedded Workshop User’s Manual ADE-702-201 Rev. 5.
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List of Items Revised or Added for This Version Section Page Description 1.2 Block Diagram 6 ASERAM deleted from figure Figure 1.1 Block Diagram BRIDGE I bus 2 UDI INTC CPG/WDT External bus interface ASERAM deleted from legend 2.5.1 Processor States 53 Description amended In the power-on reset state, the internal states of the CPU and the on-chip supporting module registers are initialized.
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Section Page Description 5.4.3 Examples of Usage 115, 116 (1) Invalidating a Specific Entry Description amended A specific cache entry can be invalidated by accessing the allocated memory cache and writing a 0 to the entry’s U and V bits. The A bit is cleared to 0, and an address is specified for the entry address and the way. If the U bit of the way of the entry in question was set to 1, the entry is written back and the V and U bits specified by the write data are written to.
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Section Page Description 8.3.3 Precautions when Using the Sleep Mode 187 Newley added 8.5.1 Transition to Module Standby Function 191 Note *3 added to bit table 9.3 Clock Operating Modes 210 Note: 3. Before putting the RTC into module standby status, first access one or more of the RTC, SCI, and TMU registers. The RTC may then be put into module standby status. The peripheral clock frequency should not be set higher than the frequency of the CKIO pin, higher than 33.34 MHz. Table 9.
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Section Page Description 10.2.13 MCS0 Control 258 Register (MCSCR0) Description added 10.3.4 Synchronous DRAM Interface 290 Bank Active description added 10.3.6 PCMCIA Interface 310 Bit 6—CS2/CS0 Select (CS2/0) Only 0 should be used for the CS2/0 bit in MCSCR0. Either 0 or 1 may be used for MCSCR1 to MCSCR7. … .In bank active mode, too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration.
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Section Page Description 16.4 SCIF Interrupts 550 Description amended When the TDFE flag in the serial status register (SCSSR) is set to 1, a TXI interrupt request is generated. The DMAC can be activated and data transfer performed when this interrupt is generated. When data exceeding the transmit trigger number is written to the transmit data register (SCFTDR) by the DMAC, 1 is read from the TDFE flag, after which 0 is written to it to clear it.
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Section Page Description 20.3 Bus Master Interface 622 Figure amended Upper byte read Figure 20.2 A/D Data Register Access Operation (Reading H'AA40) CPU receives data H'AA Module internal data bus Bus interface TEMP [H'40] ADDRn H [H'AA] ADDRn L [H'40] n = A to D Lower byte read CPU receives data H'40 Module internal data bus Bus interface TEMP [H'40] ADDRn H [H'AA] 23.1 Absolute Maximum Ratings 657 n = A to D Caution added 2.
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Section Page Description 23.3.6 Synchronous DRAM Timing 690 Tnop cycle deleted from figure Figure 23.
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Section Page A.2 Pin Specifications 723 Table A.2 Pin Specifications Description Function information amended for VCC–RTC, VCC–PLL1, VCC– PLL2, and VCC Pin A.3 Treatment of Unused Pins 724 A.4 Pin States in Access to Each Address Space 726 to 738 Pin No. (FP-208C, FP-208E) Pin No. (BP240A) I/O Function VCC– 3 RTC E2 Power supply RTC oscillator power supply (2.0/1.9/1.8/1.7 V) VCC– 145 PLL1 150 VCC– PLL2 F16, E17 Power supply PLL power supply (2.0/1.9/1.8/1.
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Contents Section 1 Overview and Pin Functions .......................................................................... 1.1 1.2 1.3 SH7709S Features ............................................................................................................. Block Diagram .................................................................................................................. Pin Description ..........................................................................................................
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3.4 3.5 3.6 3.7 MMU Functions ................................................................................................................ 3.4.1 MMU Hardware Management ............................................................................. 3.4.2 MMU Software Management............................................................................... 3.4.3 MMU Instruction (LDTLB) ................................................................................. 3.4.4 Avoiding Synonym Problems.....
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5.2 5.3 5.4 5.1.2 Cache Structure .................................................................................................... 103 5.1.3 Register Configuration ......................................................................................... 105 Register Description .......................................................................................................... 105 5.2.1 Cache Control Register (CCR) .............................................................................
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Section 7 User Break Controller ...................................................................................... 149 7.1 7.2 7.3 Overview ........................................................................................................................... 149 7.1.1 Features ................................................................................................................ 149 7.1.2 Block Diagram .....................................................................................
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8.5 8.6 8.7 8.4.1 Transition to Standby Mode ................................................................................. 188 8.4.2 Canceling Standby Mode ..................................................................................... 189 8.4.3 Clock Pause Function........................................................................................... 190 Module Standby Function ................................................................................................. 191 8.5.
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Section 10 Bus State Controller (BSC) ......................................................................... 223 10.1 Overview ........................................................................................................................... 223 10.1.1 Features ................................................................................................................ 223 10.1.2 Block Diagram ....................................................................................................
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11.2 11.3 11.4 11.5 11.6 11.1.1 Features ................................................................................................................ 327 11.1.2 Block Diagram ..................................................................................................... 329 11.1.3 Pin Configuration ................................................................................................. 330 11.1.4 Register Configuration .................................................................
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12.3 TMU Operation ................................................................................................................. 400 12.3.1 General Operation ................................................................................................ 400 12.3.2 Input Capture Function......................................................................................... 403 12.4 Interrupts ..............................................................................................................
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13.4.3 Precautions when Using RTC Module Standby ................................................... 426 Section 14 Serial Communication Interface (SCI) ..................................................... 427 14.1 Overview ........................................................................................................................... 427 14.1.1 Features ................................................................................................................ 427 14.1.2 Block Diagram ....
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15.4.1 Receive Data Timing and Receive Margin in Asynchronous Mode .................... 507 15.4.2 Retransmission (Receive and Transmit Modes) ................................................... 509 Section 16 Serial Communication Interface with FIFO (SCIF) ............................. 511 16.1 Overview ........................................................................................................................... 511 16.1.1 Features .............................................................
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18.3.1 Port A Control Register (PACR).......................................................................... 570 18.3.2 Port B Control Register (PBCR) .......................................................................... 571 18.3.3 Port C Control Register (PCCR) .......................................................................... 572 18.3.4 Port D Control Register (PDCR) .......................................................................... 573 18.3.5 Port E Control Register (PECR)........
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19.11.1 Register Description ............................................................................................. 605 19.11.2 Port K Data Register (PKDR) .............................................................................. 606 19.12 Port L................................................................................................................................. 607 19.12.1 Register Description ...........................................................................................
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Section 22 User Debugging Interface (UDI) ............................................................... 641 22.1 Overview ........................................................................................................................... 641 22.2 User Debugging Interface (UDI) ....................................................................................... 641 22.2.1 Pin Descriptions ................................................................................................... 641 22.
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A.3 A.4 Treatment of Unused Pins ................................................................................................. 724 Pin States in Access to Each Address Space ..................................................................... 725 Appendix B Memory-Mapped Control Registers....................................................... 739 B.1 B.2 Register Address Map ....................................................................................................... 739 Register Bits ....
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Figures Figure 1.1 Figure 1.2 Figure 1.3 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Figure 2.7 Figure 2.8 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 3.5 Figure 3.6 Figure 3.7 Figure 3.8 Figure 3.9 Figure 3.10 Figure 3.11 Figure 3.12 Figure 3.13 Figure 3.14 Figure 4.1 Figure 4.2 Figure 4.3 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 7.1 Figure 8.1 Figure 8.2 Block Diagram .................................
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Figure 8.3 Figure 8.4 Figure 8.5 Figure 8.6 Figure 8.7 Figure 8.8 Figure 8.9 Figure 8.10 Figure 8.11 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Figure 10.6 Figure 10.7 Figure 10.8 Figure 10.9 Figure 10.10 Figure 10.11 Figure 10.12 Figure 10.13 Figure 10.14 Figure 10.15 Figure 10.16 Figure 10.17 Figure 10.18 Figure 10.19 Figure 10.20 Figure 10.21 Figure 10.22 Figure 10.23 Figure 10.24 Figure 10.25 Figure 10.26 Figure 10.
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Figure 10.28 Figure 10.29 Figure 10.30 Figure 10.31 Figure 10.32 Figure 10.33 Figure 10.34 Figure 10.35 Figure 10.36 Figure 10.37 Figure 10.38 Figure 10.39 Figure 10.40 Figure 10.41 Figure 10.42 Figure 10.43 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Figure 11.6 Figure 11.7 Figure 11.8 Figure 11.9 Figure 11.10 Figure 11.11 Figure 11.12 Figure 11.13 Figure 11.14 Figure 11.15 Figure 11.16 Figure 11.17 Figure 11.18 Figure 11.19 Figure 11.20 Figure 11.21 Figure 11.
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Figure 11.23 Figure 11.24 Figure 11.25 Figure 11.26 Figure 11.27 Figure 11.28 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Figure 12.8 Figure 12.9 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Figure 13.6 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Figure 14.7 Figure 14.8 Figure 14.9 Figure 14.10 Figure 14.11 Figure 14.12 Figure 14.13 Figure 14.14 Figure 14.15 Figure 14.16 Timing Chart of Source Address Reload Function........
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Figure 14.17 Figure 14.18 Figure 14.19 Figure 14.20 Figure 14.21 Figure 14.22 Figure 14.23 Figure 14.24 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 Figure 15.6 Figure 15.7 Figure 15.8 Figure 15.9 Figure 15.10 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Figure 16.5 Figure 16.6 Figure 16.7 Figure 16.8 Figure 16.9 Figure 16.10 Figure 16.11 Figure 16.12 Figure 16.13 Figure 17.1 Figure 17.2 Figure 17.3 Figure 17.4 Figure 17.5 Figure 19.1 Figure 19.2 Figure 19.3 Figure 19.4 Figure 19.
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Figure 19.8 Figure 19.9 Figure 19.10 Figure 19.11 Figure 19.12 Figure 20.1 Figure 20.2 Figure 20.3 Figure 20.4 Figure 20.5 Figure 20.6 Figure 20.7 Figure 20.8 Figure 20.9 Figure 20.10 Figure 21.1 Figure 21.2 Figure 22.1 Figure 22.2 Figure 22.3 Figure 23.1 Figure 23.2 Figure 23.3 Figure 23.4 Figure 23.5 Figure 23.6 Figure 23.7 Figure 23.8 Figure 23.9 Figure 23.10 Figure 23.11 Figure 23.12 Figure 23.13 Figure 23.14 Figure 23.15 Figure 23.16 Figure 23.17 Figure 23.18 Port H ...................................
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Figure 23.19 Figure 23.20 Figure 23.21 Figure 23.22 Figure 23.23 Figure 23.24 Figure 23.25 Figure 23.26 Figure 23.27 Figure 23.28 Figure 23.29 Figure 23.30 Figure 23.31 Figure 23.32 Figure 23.33 Figure 23.34 Figure 23.35 Figure 23.36 Figure 23.37 Figure 23.38 Figure 23.39 Figure 23.40 Figure 23.41 Figure 23.42 Figure 23.43 Figure 23.44 Figure 23.45 Figure 23.46 Burst ROM Bus Cycle (No Wait) ........................................................................ 678 Burst ROM Bus Cycle (Two Waits) ........
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Figure 23.47 Figure 23.48 Figure 23.49 Figure 23.50 Figure 23.51 Figure 23.52 Figure 23.53 Figure 23.54 Figure 23.55 Figure 23.56 Figure 23.57 Figure 23.58 Figure 23.59 Figure 23.60 Figure D.1 Figure D.2 Figure D.3 TCLK Input Timing ............................................................................................. 707 TCLK Clock Input Timing................................................................................... 707 Oscillation Settling Time at RTC Crystal Oscillator Power-on.........
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Tables Table 1.1 Table 1.2 Table 1.3 Table 2.1 Table 2.2 Table 2.3 Table 2.4 Table 2.5 Table 2.6 Table 2.7 Table 2.8 Table 2.9 Table 2.10 Table 2.11 Table 2.12 Table 3.1 Table 3.2 Table 4.1 Table 4.2 Table 4.3 Table 4.4 Table 5.1 Table 5.2 Table 5.3 Table 5.4 Table 5.5 Table 5.6 Table 5.7 Table 5.8 Table 6.1 Table 6.2 Table 6.3 Table 6.4 Table 6.5 Table 6.6 Table 6.7 Table 6.8 Table 7.1 Table 7.2 Table 8.1 SH7709S Features ....................................................................................
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Table 8.2 Table 8.3 Table 8.4 Table 9.1 Table 9.2 Table 9.3 Table 9.4 Table 9.5 Table 10.1 Table 10.2 Table 10.3 Table 10.4 Table 10.5 Table 10.6 Table 10.7 Table 10.8 Table 10.9 Table 10.10 Table 10.11 Table 10.12 Table 10.13 Table 10.14 Pin Configuration.................................................................................................... 183 Register Configuration............................................................................................
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Table 13.2 Table 13.3 Table 13.4 Table 13.5 Table 14.1 Table 14.2 Table 14.3 Table 14.4 Table 14.5 Table 14.6 Table 14.7 Table 14.8 Table 14.9 Table 14.10 Table 14.11 Table 14.12 Table 14.13 Table 14.14 Table 15.1 Table 15.2 Table 15.3 Table 15.4 Table 15.5 Table 15.6 Table 15.7 Table 15.8 Table 15.9 Table 16.1 Table 16.2 Table 16.3 Table 16.4 Table 16.5 Table 16.6 Table 16.7 Table 16.8 Table 16.9 Table 16.10 Table 17.1 Table 17.2 Table 18.1 Table 18.2 RTC Registers.........................................
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Table 19.1 Table 19.2 Table 19.3 Table 19.4 Table 19.5 Table 19.6 Table 19.7 Table 19.8 Table 19.9 Table 19.10 Table 19.11 Table 19.12 Table 19.13 Table 19.14 Table 19.15 Table 19.16 Table 19.17 Table 19.18 Table 19.19 Table 19.20 Table 19.21 Table 19.22 Table 19.23 Table 19.24 Table 20.1 Table 20.2 Table 20.3 Table 20.4 Table 20.5 Table 20.6 Table 21.1 Table 21.2 Table 22.1 Table 22.2 Table 22.3 Table 22.4 Table 23.1 Table 23.2 Table 23.3 Table 23.4 Table 23.5 Table 23.6 Table 23.7 Port A Register .......
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Table 23.8 Table 23.9 Table 23.10 Table 23.11 Table A.1 Table A.2 Table A.3 Table A.4 Table A.5 Table A.6 Table A.7 Table A.8 Table A.9 Table A.10 Table B.1 Table B.2 Table C.1 Peripheral Module Signal Timing........................................................................... 706 UDI-Related Pin Timing......................................................................................... 709 A/D Converter Characteristics..............................................................................
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Rev. 5.
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Section 1 Overview and Pin Functions 1.1 SH7709S Features This LSI is a single-chip RISC microprocessor that integrates a Renesas Technology-original RISC-type SuperHTM architecture CPU as its core that has an on-chip multiplier, cache memory, and a memory management unit (MMU) as well as peripheral functions required for system configuration such as a timer, a realtime clock, an interrupt controller, and a serial communication interface.
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Table 1.
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Item Features Cache memory • 16-kbyte cache, mixed instruction/data • 256 entries, 4-way set associative, 16-byte block length • Write-back, write-through, LRU replacement algorithm • 1-stage write-back buffer • Maximum 2 ways of the cache can be locked Interrupt controller (INTC) • 23 external interrupt pins (NMI, IRQ5–IRQ0, PINT15 to PINT0) • On-chip peripheral interrupts: set priority levels for each module User break controller (UBC) • 2 break channels • Addresses, data values, typ
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Item Features Serial communi- • cation interface 0 • (SCI0/SCI) • Asynchronous mode or clock synchronous mode can be selected Serial communi- • cation interface 1 • (SCI1/IrDA) • 16-byte FIFO for transmission/reception Serial communi- • cation interface 2 • (SCI2/SCIF) • 16-byte FIFO for transmission/reception Direct memory • access controller • (DMAC) • 4 channels Full-duplex communication Supports smart card interface DMA can be transferred IrDA: interface based on 1.
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Table 1.2 Characteristics Item Characteristics Power supply voltage • I/O: 3.3 ±0.3 V Internal: 2.0 ±0.15 V (200 MHz model)*, 1.9±0.15 V (167 MHz model), 1.8 (+0.25, –0.15) V (133 MHz model), 1.7(+0.25, –0.15) V (100 MHz model) Operating frequency • Internal frequency: maximum 200 MHz(200 MHz model), 167 MHz (167 MHz model) 133.34 MHz (133 MHz model), 100 MHz (100 MHz model); external frequency: maximum 66.67 MHz Process • 0.25-µm CMOS/5-layer metal Note: * 2.0 (+0.15, –0.
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1.
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Pin Description 1.3.
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A B C D E F G H J K L M N P R T U V W 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 SH7709S 11 10 BP-240A 10 9 (Top view) 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 A B C D E F G H J K L M N P R T U Note: The pin area enclosed in broken lines is an inner view. Figure 1.3 Pin Assignment (BP-240A) Rev. 5.
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1.3.2 Table 1.
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Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 27 K3 Vss — Power supply (0 V) — K4 Vss — Power supply (0 V) 28 K1 D19/PTA[3] I/O 29 L3 Vcc — Data bus / input/output port A 3 Power supply (1.9 V/1.
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Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 57 U4 VssQ — Input/output power supply (0 V) 58 W5 A4 O Address bus 59 U3 VccQ — Input/output power supply (3.
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Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 87 W12 BS/PTK[4] O / I/O Bus cycle start signal / input/output port K 88 T13 RD O Read strobe 89 U13 WE0/DQMLL O D7–D0 select signal / DQM (SDRAM) 90 V13 WE1/DQMLU/WE O D15–D8 select signal / DQM (SDRAM) 91 W13 WE2/DQMUL/ICIORD/ PTK[6] O / I/O D23–D16 select signal / DQM (SDRAM) / PCMCIA I/O read / input/output port K 92 T14 WE3/DQMUU/ICIOWR/ O / I/O PTK[7] D31–D24 select signal / DQM (SDRAM) / PCMCIA I/O write
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Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 106 U18 RAS3L/PTJ[0] O / I/O 107 U19 PTJ[1] O / I/O Lower 32 M / 64 Mbytes address (SDRAM) RAS / input/output port J 5 Input/output port J* 108 R18 CASL/PTJ[2] O / I/O Lower 32 M / 64 Mbytes address (SDRAM) CAS / input/output port J 109 T19 VssQ — Input/output power supply (0 V) 110 T17 CASU/PTJ[3] O / I/O Lower 32 Mbytes address (SDRAM) CAS / input/output port J 111 R19 VccQ — Input/output power supply (3.
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Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 130 L17 AUDATA[3]/PTG[3] I/O / I AUD data / input port G 131 K18 AUDATA[2]/PTG[2] I/O/I AUD data / input port G 132 K17 Vss — Power supply (0 V) — K16 Vss — Power supply (0 V) 133 K19 AUDATA[1]/PTG[1] I/O / I 134 J17 Vcc — AUD data / input port G 3 Power supply (* ) — J16 Vcc — Power supply (* ) 135 J18 AUDATA[0]/PTG[0] I/O / I AUD data / input port G 136 J19 TRST/PTF[7]/PINT[15] I Test reset / in
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Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description — D19 Vss — 154 E18 Vcc — Power supply (0 V) 3 Power supply (* ) — C19 Vcc — Power supply (* ) 155 C18 XTAL O Clock oscillator pin 156 D18 EXTAL I External clock / crystal oscillator pin 157 B16 STATUS0/PTJ[6] O / I/O Processor status / input/output port J 158 B17 STATUS1/PTJ[7] O / I/O Processor status / input/output port J 159 B15 TCLK/PTH[7] I/O TMU or RTC clock input/output / input/output port H 1
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Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 176 A11 CTS2/IRQ5/SCPT[7] I Transmit clear 2 / external interrupt request / SCI input port 177 B11 MCS[7]/PTC[7]/PINT[7] O / I/O / I Mask ROM chip select / input/output port C / port interrupt 178 D11 MCS[6]/PTC[6]/PINT[6] O / I/O / I Mask ROM chip select / input/output port C / port interrupt 179 C11 MCS[5]/PTC[5]/PINT[5] O / I/O / I Mask ROM chip select / input/output port C / port interrupt 180 B10 MCS[4]/PTC[4]/PINT[
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Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 198 B6 AVss — Analog power supply (0 V) 199 A6 AN[0]/PTL[0] I A/D converter input / input port L 200 D5 AN[1]/PTL[1] I A/D converter input / input port L 201 C5 AN[2]/PTL[2] I A/D converter input / input port L 202 D4 AN[3]/PTL[3] I A/D converter input / input port L 203 A5 AN[4]/PTL[4] I A/D converter input / input port L 204 C4 AN[5]/PTL[5] I A/D converter input / input port L 205 A4 AVcc — Analog p
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Rev. 5.
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Section 2 CPU 2.1 Register Configuration 2.1.1 Privileged Mode and Banks Processor Modes: There are two processor modes: user mode and privileged mode. The SH7709S normally operates in user mode, and enters privileged mode when an exception occurs or an interrupt is accepted. There are three kinds of registers—general registers, system registers, and control registers—and the registers that can be accessed differ in the two processor modes.
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31 R0_BANK0*1 *2 R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2 R8 R9 R10 R11 R12 R13 R14 R15 0 SR GBR MACH MACL PR PC User mode register configuration Notes: 1. R0 functions as an index register in the indexed register-indirect addressing mode and indexed GBR-indirect addressing mode. 2. Banked register. Figure 2.1 User Mode Register Configuration Rev. 5.
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31 0 31 0 R0_BANK1*1 *2 R1_BANK1*2 R2_BANK1*2 R3_BANK1*2 R4_BANK1*2 R5_BANK1*2 R6_BANK1*2 R7_BANK1*2 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0*1 *3 R1_BANK0*3 R2_BANK0*3 R3_BANK0*3 R4_BANK0*3 R5_BANK0*3 R6_BANK0*3 R7_BANK0*3 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR SR SSR GBR MACH MACL PR VBR GBR MACH MACL PR VBR PC SPC PC SPC R0_BANK0*1 *3 R1_BANK0*3 R2_BANK0*3 R3_BANK0*3 R4_BANK0*3 R5_BANK0*3 R6_BANK0*3 R7_BANK0*3 R0_BANK1*1 *2 R1_BANK1*2 R2_BANK1*2 R3_BANK1*2 R4_BANK1*2 R5_BANK1*2 R6_BANK1*2 R7_BAN
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Register values after a reset are shown in table 2.1. Table 2.1 Initial Register Values Type Registers Initial Value* General registers R0 to R15 Undefined Control registers SR MD bit = 1, RB bit = 1, BL bit = 1, I3–I0 = 1111 (H'F), reserved bits = 0, others undefined GBR, SSR, SPC Undefined VBR H'00000000 MACH, MACL, PR Undefined PC H'A0000000 System registers Note: * Register values are initialized at power-on reset or manual reset. 2.1.
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2.1.3 System Registers System registers can be accessed by the LDS and STS instructions. When an exception occurs, the contents of the program counter (PC) are saved in the saved program counter (SPC). The SPC contents are restored to the PC by the RTE instruction used at the end of the exception handling. There are four system registers, as follows.
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SSR 0 Saved Status Register (SSR) Stores current SR value at time of exception to indicate processor status in return to instruction stream from exception handler. SPC 0 Saved Program Counter (SPC) Stores current PC value at time of exception to indicate return address at completion of exception handling. 31 31 31 GBR 31 VBR 0 Global Base Register (GBR) Stores base address of GBR-indirect addressing mode.
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2.2 Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits, figure 2.6). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 31 0 Longword Figure 2.6 Longword 2.2.2 Data Format in Memory Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword form.
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2.3 Instruction Features 2.3.1 Execution Environment Data Length: The SH7709S instruction set is implemented with fixed-length 16-bit wide instructions executed in a pipelined sequence with single-cycle execution for most instructions. All operations are executed in 32-bit longword units. Memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword units, with byte or word units sign-extended into 32-bit longwords.
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T bit: The T bit in the status register (SR) is used to indicate the result of compare operations, and is read as a TRUE/FALSE condition determining if a conditional branch is taken or not. To improve processing speed, the T bit logic state is modified only by specific operations. An example of how the T bit may be used in a sequence of operations is shown below.
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2.3.2 Addressing Modes Addressing modes and effective address calculation methods are shown in table 2.2. Table 2.2 Addressing Mode Addressing Modes and Effective Addresses Instruction Format Effective Address Calculation Method Calculation Formula Register direct Rn Effective address is register Rn. (Operand is register Rn contents.) — Register indirect Effective address is register Rn contents.
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Addressing Mode Instruction Format Effective Address Calculation Method Register indirect with displacement @(disp:4, Rn) Effective address is register Rn contents with 4-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size.
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Addressing Mode Instruction Format Effective Address Calculation Method PC-relative with displacement @(disp:8, PC) Effective address is register PC contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 2 (word), or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked.
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Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula PC-relative Rn PC + Rn Effective address is sum of register PC and Rn contents. PC + PC + R0 R0 Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. — #imm:8 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. — #imm:8 8-bit immediate data imm of TRAPA — instruction is zero-extended and multiplied by 4.
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2.3.3 Instruction Formats Table 2.3 explains the meaning of instruction formats and source and destination operands. The meaning of the operands depends on the operation code. The following symbols are used. xxxx: mmmm: nnnn: iiii: dddd: Table 2.
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Source Operand Instruction Format nm format 15 xxxx nnnn mmmm xxxx md format 15 xxxx xxxx mmmm dddd xxxx dddd nd4 format 15 xxxx nnnn Destination Operand Instruction Example 0 mmmm: register direct nnnn: register direct ADD mmmm: register indirect nnnn: register indirect MOV.L Rm,@Rn mmmm: register indirect with postincrement (multiply-andaccumulate operation) nnnn: * register indirect with postincrement (multiply-andaccumulate operation) MACH,MACL MAC.
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Source Operand Instruction Format nmd format 15 xxxx nnnn mmmm dddd Destination Operand Instruction Example nnnndddd: register indirect with displacement MOV.L Rm,@(disp,Rn) nnnn: register direct MOV.L @(disp,Rm),Rn R0 (register direct) MOV.L @(disp,GBR),R 0 R0 (register direct) dddddddd: GBR indirect with displacement MOV.
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2.4 Instruction Set 2.4.1 Instruction Set Classified by Function The SH7709S instruction set includes 68 basic instruction types, as listed in table 2.4. Table 2.4 Classification of Instructions Classification Types Operation Code Function No.
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Classification Types Arithmetic operations (cont) Logic operations Shift 21 6 12 Operation Code Function MUL Double-precision multiplication (32 × 32 bits) MULS Signed multiplication (16 × 16 bits) MULU Unsigned multiplication (16 × 16 bits) NEG Negation NEGC Negation with borrow SUB Binary subtraction SUBC Binary subtraction with borrow SUBV Binary subtraction with underflow check AND Logical AND NOT Bit inversion OR Logical OR TAS Memory test and bit set TST Logical AND and
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Classification Types Operation Code Branch BF Conditional branch, delayed conditional branch (T = 0) BT Conditional branch, delayed conditional branch (T = 1) BRA Unconditional branch BRAF Unconditional branch BSR Branch to subroutine procedure BSRF Branch to subroutine procedure JMP Unconditional branch JSR Branch to subroutine procedure RTS Return from subroutine procedure System control 9 15 Total: 68 No.
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Table 2.5 lists the SH7709S instruction code formats. Table 2.5 Instruction Code Format Item Format Explanation Instruction mnemonic OP.Sz SRC,DEST OP: Operation code Sz: Size SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement Instruction code MSB ↔ LSB mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 ...........
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Table 2.6 lists the SH7709S data transfer instructions Table 2.6 Data Transfer Instructions Instruction Operation Code Privileged Mode Cycles T Bit MOV #imm,Rn imm → Sign extension → Rn 1110nnnniiiiiiii — 1 — MOV.W @(disp,PC),Rn (disp × 2 + PC) → Sign extension → Rn 1001nnnndddddddd — 1 — MOV.L @(disp,PC),Rn (disp × 4 + PC) → Rn 1101nnnndddddddd — 1 — MOV Rm,Rn Rm → Rn 0110nnnnmmmm0011 — 1 — MOV.B Rm,@Rn Rm → (Rn) 0010nnnnmmmm0000 — 1 — MOV.
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Instruction Operation Code Privileged Mode Cycles T Bit MOV.W Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0101 — MOV.L Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0110 — 1 — MOV.B @(R0,Rm),Rn (R0 + Rm) → Sign extension → Rn 0000nnnnmmmm1100 — 1 — MOV.W @(R0,Rm),Rn (R0 + Rm) → Sign extension → Rn 0000nnnnmmmm1101 — 1 — MOV.L @(R0,Rm),Rn (R0 + Rm) → Rn 0000nnnnmmmm1110 — 1 — MOV.B R0,@(disp,GBR) R0 → (disp + GBR) 11000000dddddddd — 1 — MOV.
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Table 2.7 lists the SH7709S arithmetic instructions. Table 2.
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Instruction Operation Code Privileged Mode Cycles T Bit DMULS.L Rm,Rn Signed operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits 0011nnnnmmmm1101 — 2(to 5)* — DMULU.L Rm,Rn Unsigned operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits 0011nnnnmmmm0101 — 2(to 5)* — DT Rn – 1 → Rn, if Rn = 0, 1 → T, else 0 → T 0100nnnn00010000 — 1 Comparison result EXTS.B Rm,Rn A byte in Rm is signextended → Rn 0110nnnnmmmm1110 — 1 — EXTS.
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Instruction Operation Code Privileged Mode Cycles T Bit NEG Rm,Rn 0–Rm → Rn 0110nnnnmmmm1011 — 1 — NEGC Rm,Rn 0–Rm–T → Rn, Borrow → T 0110nnnnmmmm1010 — 1 Borrow SUB Rm,Rn Rn–Rm → Rn 0011nnnnmmmm1000 — 1 — SUBC Rm,Rn Rn–Rm–T → Rn, Borrow → T 0011nnnnmmmm1010 — 1 Borrow SUBV Rm,Rn Rn–Rm → Rn, Underflow → T 0011nnnnmmmm1011 — 1 Underflow Note: * The normal number of execution cycles is shown.
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Table 2.8 lists the SH7709S logic operation instructions. Table 2.8 Logic Operation Instructions Instruction Operation Code Privileged Mode Cycles T Bit AND Rm,Rn Rn & Rm → Rn 0010nnnnmmmm1001 — 1 — AND #imm,R0 R0 & imm → R0 11001001iiiiiiii — 1 — AND.B #imm,@(R0,GBR) (R0 + GBR) & imm → (R0 + GBR) 11001101iiiiiiii — 3 — NOT Rm,Rn ~Rm → Rn 0110nnnnmmmm0111 — 1 — OR Rm,Rn Rn | Rm → Rn 0010nnnnmmmm1011 — 1 — OR #imm,R0 R0 | imm → R0 11001011iiiiiiii — 1 — OR.
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Table 2.9 lists the SH7709S shift instructions. Table 2.
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Table 2.10 lists the SH7709S branch instructions. Table 2.
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Table 2.11 lists the SH7709S system control instructions. Table 2.
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Instruction Operation Code Privileged Mode Cycles T Bit LDC.L @Rm+, R6_BANK (Rm) → R6_BANK, Rm + 4 → Rm 0100mmmm11100111 √ 5 — LDC.L @Rm+, R7_BANK (Rm) → R7_BANK, Rm + 4 → Rm 0100mmmm11110111 √ 5 — LDS Rm,MACH Rm → MACH 0100mmmm00001010 — 1 — LDS Rm,MACL Rm → MACL 0100mmmm00011010 — 1 — LDS Rm,PR Rm → PR 0100mmmm00101010 — 1 — LDS.L @Rm+,MACH (Rm) → MACH, Rm + 4 → Rm 0100mmmm00000110 — 1 — LDS.L @Rm+,MACL (Rm) → MACL, Rm + 4 → Rm 0100mmmm00010110 — 1 — LDS.
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Instruction Operation Code Privileged Mode Cycles T Bit STC.L SSR,@–Rn Rn–4 → Rn, SSR → (Rn) 0100nnnn00110011 √ 2 — STC.L SPC,@–Rn Rn–4 → Rn, SPC → (Rn) 0100nnnn01000011 √ 2 — STC.L R0_BANK, @–Rn Rn–4 → Rn, R0_BANK → (Rn) 0100nnnn10000011 √ 2 — STC.L R1_BANK, @–Rn Rn–4 → Rn, R1_BANK → (Rn) 0100nnnn10010011 √ 2 — STC.L R2_BANK, @–Rn Rn–4 → Rn, R2_BANK → (Rn) 0100nnnn10100011 √ 2 — STC.L R3_BANK, @–Rn Rn–4 → Rn, R3_BANK → (Rn) 0100nnnn10110011 √ 2 — STC.
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2.4.2 Instruction Code Map Table 2.12 shows the instruction code map. Table 2.
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Instruction Code MSB 0100 Rn Fx: 0000 MD: 00 LSB Fx 0000 SHLL Rn Fx: 0001 MD: 01 DT Rn Fx: 0010 MD: 10 SHAL Fx: 0011 to 1111 MD: 11 Rn 0100 Rn Fx 0001 SHLR Rn CMP/PZ Rn SHAR Rn 0100 Rn Fx 0010 STS.L MACH,@-Rn STS.L MACL,@-Rn STS.L PR,@-Rn 0100 Rn 00MD 0011 STC.L SR,@-Rn STC.L GBR,@-Rn STC.L VBR,@-Rn STC.L SSR,@-Rn 0100 Rn 01MD 0011 STC.L SPC,@-Rn 0100 Rn 10MD 0011 STC.L R0_BANK,@-Rn STC.L R1_BANK,@-Rn STC.L R2_BANK,@-Rn STC.L R3_BANK,@-Rn 0100 Rn 11MD 0011 STC.
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Instruction Code MSB Fx: 0000 MD: 00 LSB Fx: 0001 MD: 01 1000 00MD Rn disp MOV.B R0,@(disp:4,Rn) MOV.W R0,@(disp:4,Rn) 1000 01MD Rm disp MOV.B @(disp:4,Rm),R0 MOV.W @(disp:4,Rm),R0 1000 10MD imm/disp CMP/EQ #imm:8,R0 1000 11MD imm/disp 1001 Rn disp Fx: 0010 MD: 10 Fx: 0011 to 1111 MD: 11 BT label:8 BF label:8 BT/S label:8 BF/S label:8 #imm:8 MOV.W @(DISP:8,PC),RN 1010 disp BRA label:12 1011 disp BSR label:12 1100 00MD imm/disp MOV.B R0,@(disp:8,GBR) MOV.
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2.5 Processor States and Processor Modes 2.5.1 Processor States The SH7709S has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state. Reset State: In this state the CPU is reset. The CPU enters the power-on reset state if the RESETP pin is low, or the manual reset state if the RESETM pin is low. See section 4, Exception Handling, for more information on resets.
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From any state when RESETP = 0 From any state but hardware standby mode when RESETM = 0 RESETP = 0 Power-on reset state Manual reset state Reset state RESETP = 1 RESETM = 1 Exception-handling state Interrupt Bu sr eq st ue u eq sr Bu Bus-released state Bus request ce ran ea cl est Exception interrupt End of exception transition processing Bu cle s requ ara nce est Bus req Program execution state ues t Bus request clearance SLEEP instruction with STBY bit cleared Interrupt SLEEP in
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Section 3 Memory Management Unit (MMU) 3.1 Overview 3.1.1 Features The SH7709S has an on-chip memory management unit (MMU) that implements address translation. The SH7709S features a resident translation look-aside buffer (TLB) that caches information for user-created address translation tables located in external memory. It enables highspeed translation of virtual addresses into physical addresses. Address translation uses the paging system and supports two page sizes (1 kbytes and 4 kbytes).
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case, the MMU will generate an exception, change the physical memory mapping, and record the new address translation information. Although the functions of the MMU could also be implemented by software alone, the need for translation to be performed by software each time a process accesses physical memory would result in poor efficiency. For this reason, a buffer for address translation (translation look-aside buffer: TLB) is provided in hardware to hold frequently used address translation information.
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Virtual memory Process 1 Physical memory Process 1 MMU Physical memory Physical memory Process 1 (2) (1) Process 1 Process 1 Virtual memory MMU Physical memory Physical memory Process 2 Process 2 Process 3 Process 3 (3) (4) Figure 3.1 MMU Functions Rev. 5.
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3.1.3 SH7709S MMU Virtual Address Space: The SH7709S uses 32-bit virtual addresses to access a 4-Gbyte virtual address space that is divided into several areas. Address space mapping is shown in figure 3.2. • Privileged Mode In privileged mode, there are five areas, P0–P4. The P0 and P3 areas are mapped onto physical address space in page units, in accordance with address translation table information.
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H'00000000 H'00000000 2-Gbyte virtual space, cacheable (write-back/write-through) H'80000000 H'A0000000 H'C0000000 H'E0000000 Area U0 H'80000000 0.5-Gbyte fixed physical space, cacheable (write-back/write-through) Area P1 0.5-Gbyte fixed physical space, non-cacheable Area P2 0.5-Gbyte virtual space, cacheable (write-back/write-through) Area P3 0.
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If the virtual address is not registered in the TLB, a TLB miss exception occurs and processing will shift to the TLB miss handler. In the TLB miss handler, the TLB address translation table in external memory is searched and the corresponding physical address and the page control information are registered in the TLB. After returning from the handler, the instruction that caused the TLB miss is re-executed.
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3.1.4 Register Configuration A register that has an undefined initial value must be initialized by software. Table 3.1 shows the configuration of the MMU control registers. Table 3.
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5. The MMU control register (MMUCR) residing at address H'FFFFFFE0, which makes the MMU settings described in figure 3.3. Any program that modifies MMUCR should reside in the P1 or P2 area. The MMU registers are shown in figure 3.3. 31 10 VPN 7 0 0 ASID PTEH 31 29 28 10 9 8 7 6 000 PPN 0 V* 0 4 3 2 1 0 PR* SZ* C* D* SH* 0 PTEL 31 0 TTB TTB 31 0 Virtual address causing TLB-related or address error exception TEA 31 8 0 7 6543 2 1 0 SV 00 RC 0 TF IX AT MMUCR 0: Reserved bits.
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3.3 TLB Functions 3.3.1 Configuration of the TLB The TLB caches address translation table information located in the external memory. The address translation table stores the physical page number translated from the virtual page number and the control information for the page, which is the unit of address translation. Figure 3.4 shows the overall TLB configuration. The TLB is 4-way set associative with 128 entries. There are 32 entries for each way. Figure 3.
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31 10 9 VPN 0 Offset Virtual address (1-kbyte page) 12 11 31 VPN 0 Offset Virtual address (4-kbyte page) (15) (2) (8) VPN (31–17) VPN (11–10) ASID (1) (19) (2) (1) (1) (1) (1) V PPN PR SZ C SH D TLB entry Legend: VPN: Virtual page number. Top 22 bits of virtual address for a 1-kbyte page, or top 20 bits of virtual address for a 4-kbyte page. Since VPN bits 16-12 are used as the index number, they are not stored in the TLB entry. ASID: Address space identifier.
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3.3.2 TLB Indexing The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16 to 12 and ASID bits 4 to 0 in PTEH are used as the index number regardless of the page size. The index number can be generated in two different ways depending on the setting of the IX bit in MMUCR. 1. When IX = 0, VPN bits 16–12 alone are used as the index number 2.
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Virtual address 31 17 16 12 11 0 Index Ways 0−3 0 VPN(31−17) VPN(11−10) ASID(7−0) V PPN(28−10) PR(1−0) SZ C D SH 31 Address array Data array Figure 3.7 TLB Indexing (IX = 0) 3.3.3 TLB Address Comparison The results of address comparison determine whether a specific virtual page number is registered in the TLB. The virtual page number of the virtual address that accesses external memory is compared to the virtual page number of the indexed TLB entry.
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The sharing information (SH) determines whether the PTEH.ASID and the ASID in the TLB entry are compared. ASIDs are compared when there is no sharing between processes (SH = 0) but not when there is sharing (SH = 1). When single virtual memory is supported (MMUCR.SV = 1) and privileged mode is engaged (SR.MD = 1), all process resources can be accessed. This means that ASIDs are not compared when single virtual memory is supported and privileged mode is engaged.
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3.3.4 Page Management Information In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and PR bits. The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit is 0, an attempt to write to the page results in an initial page write exception.
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3.4 MMU Functions 3.4.1 MMU Hardware Management There are two kinds of MMU hardware management as follows: 1. The MMU decodes the virtual address accessed by a process and performs address translation by controlling the TLB in accordance with the MMUCR settings. 2. In address translation, the MMU receives page management information from the TLB, and determines the MMU exception and whether the cache is to be accessed (using the C bit).
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3.4.3 MMU Instruction (LDTLB) The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is 0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR to the value specified by PTEH and PTEL, using VPN bits 16–12 specified in PTEH as the index number. When the IX bit in MMUCR is 1, the EX-OR of VPN bits 16–12 specified in PTEH and ASID bits 4–0 in PTEH are used as the index number. Figure 3.9 shows the case where the IX bit in MMUCR is 0.
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MMUCR 31 9 0 0 SV 0 0 RC 0 TF IX AT Way selection Index PTEH register 31 17 VPN 12 10 VPN 8 0 PTEL register 31 29 28 10 0 000 ASID PPN 0 0 V 0 PR SZ C D SH 0 Write Write Ways 0 to 3 0 VPN(31−17) VPN(11−10) ASID(7−0) V PPN(28−10) PR(1−0) SZ C D SH 31 Address array Data array Figure 3.9 Operation of LDTLB Instruction Rev. 5.
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3.4.4 Avoiding Synonym Problems When a 1-kbyte page is recorded in a TLB entry, a synonym problem may arise. If a number of virtual addresses are mapped onto a single physical address, the same physical address data will be recorded in a number of cache entries, and it will not be possible to guarantee data congruity. The reason why this problem only occurs when using a 1-kbyte page is explained below with reference to figure 3.10.
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When using a 4-kbyte page Virtual address 0 12 11 10 31 VPN Offset Virtual address (11−4) Physical address 31 29 28 PPN 000 0 12 11 10 Cache address array Offset Physical address (28−10) When using a 1-kbyte page Virtual address 11 10 9 31 VPN Virtual address (11−4) Physical address 31 29 28 000 PPN 0 Offset 11 10 9 0 Cache address array Offset Physical address (28−10) Figure 3.10 Synonym Problem Rev. 5.
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3.5 MMU Exceptions There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial page write. 3.5.1 TLB Miss Exception A TLB miss results when the virtual address and the address array of the selected TLB entry are compared and no match is found. TLB miss exception processing includes both hardware and software operations. Hardware Operations: In a TLB miss, the SH7709S hardware executes a set of prescribed operations, as follows: 1.
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2. If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 4. Issue the return from exception handler (RTE) instruction to terminate the handler routine and return to the instruction stream. 3.5.
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3.5.3 TLB Invalid Exception A TLB invalid exception results when the virtual address is compared to a selected TLB entry address array and a match is found but the entry is not valid (the V bit is 0). TLB invalid exception processing includes both hardware and software operations. Hardware Operations: In a TLB invalid exception, the SH7709S hardware executes a set of prescribed operations, as follows: 1. The VPN number of the virtual address causing the exception is written to the PTEH register. 2.
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3.5.4 Initial Page Write Exception An initial page write exception results in a write access when the virtual address and the address array of the selected TLB entry are compared and a valid entry with the appropriate access rights is found to match, but the D (dirty) bit of the entry is 0 (the page has not been written to). Initial page write exception processing includes both hardware and software operations.
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Start SH = 0 and (MMUCR.SV = 0 or SR.MD = 0)? No No Yes VPNs match? VPNs and ASIDs match? No Yes Yes No V = 1? TLB miss exception TLB invalid exception Yes User mode Privileged mode User or privileged? PR check 00/01 W 10 R/W? R PR check 11 R/W? 01/11 W W R No R/W? 00/10 W R/W? R R D = 1? Yes TLB protection violation exception Initial page write exception No (noncacheable) Memory access TLB protection violation C = 1? Yes (cacheable) Cache access Figure 3.
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3.5.5 Processing Flow in Event of MMU Exception (Same Processing Flow for Address Error) Figure 3.12 shows the MMU exception signals in the instruction fetch mode. IF ID EX MA WB ID EX MA ID EX Handler transition processing WB MA WB NOP NOP MMU exception handler IF ID EX MA WB : Exception source stage IF ID EX MA WB NOP = Instruction fetch = Instruction decode = Instruction execution = Memory access = Write back = No operation Figure 3.
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Figure 3.13 shows the MMU exception signals in the data access mode. IF ID EX MA WB IF ID EX MA WB IF ID EX MA WB ID EX MA WB ID EX MA WB ID EX MA WB Handler transition processing NOP NOP MMU exception handler IF ID EX MA WB : Exception source stage : Stage cancellation for instruction that has begun execution IF ID EX MA WB NOP = Instruction fetch = Instruction decode = Instruction execution = Memory access = Write back = No operation Figure 3.
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In the address field, specify VPN in bits 16-12 as the index address that selects the entry, W in bits 9-8 to select the way, and H'F2 in bits 31-24 to indicate access to the address array. Selection of the index address depends on the MMUCR.IX setting. The following 2 types of operations on the address array are possible. (1) Address Array Read Reads VPN, V bit, and ASID from the entry that corresponds to the entry address and way that were specified in the address field.
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(1) TLB Address Array Access Read access 17 16 24 23 31 Address field 11110010 * * 17 16 31 Data field VPN 12 11 10 9 8 7 6 VPN * * W 0 0 * * 12 11 10 9 8 7 0 0 VPN 0 V 0 ASID Write access 31 Address field 24 23 11110010 17 16 * * 17 16 31 Data field * * W 0 0 * * 12 11 10 9 8 7 * VPN VPN: V: W: 12 11 10 9 8 7 6 VPN * VPN * V 0 ASID Virtual page number ASID: Address space identifier Valid bit * : Don't care bit Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3) (2) TLB Data
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3.6.3 Usage Examples Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry’s V bit. When the A bit is 1, the VPN and ASID specified by the write data is compared to the VPN and ASID within the TLB entry selected by the entry address and data is written to the matching way. If no match is found, there is no operation. R0 specifies the write data and R1 specifies the address. ; R0=H'1547 381C R1=H'F201 3000 ; MMUCR.
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Rev. 5.
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Section 4 Exception Handling 4.1 Overview 4.1.1 Features Exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. In response to an exception handling request due to abnormal termination of the executing instruction, control is passed to a user-written exception handler. However, in response to an interrupt request, normal program execution continues until the end of the executing instruction.
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contents of PC and SR to return to the processor state at the point of interruption and the address where the exception occurred. A basic exception handling sequence consists of the following operations: 1. The contents of PC and SR are saved in SPC and SSR, respectively. 2. The block (BL) bit in SR is set to 1, masking any subsequent exceptions. 3. The mode (MD) bit in SR is set to 1 to place the SH7709S in privileged mode. 4. The register bank (RB) bit in SR is set to 1. 5.
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Table 4.
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4.2.3 Acceptance of Exceptions Processor resets and interrupts are asynchronous events unrelated to the instruction stream. All exception events are prioritized to establish an acceptance order whenever two or more exception events occur simultaneously. All general exception events occur in a relative order in the execution sequence of an instruction (i.e. execution order), but are handled at priority level 2 in instruction-stream order (i.e.
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Pipeline Sequence: Instruction n IF ID EX MA WB TLB miss (data access) Instruction n + 1 IF ID EX MA WB TLB miss (instruction access) Instruction n + 2 IF ID EX MA WB RIE (reserved instruction exception) Detection Order: TLB miss (instruction n+1) TLB miss (instruction n) and general illegal instruction exception (instruction n + 2) = simultaneous detection Handling Order: Program Order: TLB miss (instruction n) 1 Re-execution of instruction n TLB miss (instruction n + 1) 2 Re-executio
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instruction or delay slot is accepted after execution of the delayed branch instruction. The delay slot here refers either to the next instruction after a delayed unconditional branch instruction or to the next instruction when a delayed conditional branch instruction is true. 4.2.4 Exception Codes Table 4.
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Exception Type Exception Event General interrupt requests (cont) External hardware interrupts (cont): 4.2.
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4.3 Register Descriptions There are four registers related to exception handling. These are peripheral module registers, and therefore reside in area P4. They can be accessed by specifying the address in privileged mode only. 1. The exception event register (EXPEVT) resides at address H'FFFFFFD4, and contains a 12-bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when an exception occurs.
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4.4 Exception Handling Operation 4.4.1 Reset The reset sequence is used to power up or restart the SH7709S from the initialization state. The RESETP and RESETM signals are sampled every clock cycle, and in the case of a power-on reset, all processing being executed (excluding the RTC) is suspended, all unfinished events are canceled, and reset processing is executed immediately. In the case of a manual reset, however, reset processing is executed after completion of any memory access being executed.
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4.4.3 General Exceptions When the SH7709S encounters any exception condition other than a reset or interrupt request, it executes the following operations: 1. The contents of PC and SR are saved to SPC and SSR, respectively. 2. The BL bit in SR is set to 1, masking any subsequent exceptions (except the NMI interrupt when the BLMSK bit is 1). 3. The MD bit in SR is set to 1 to place the SH7709S in privileged mode. 4. The RB bit in SR is set to 1. 5.
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• UDI Reset  Conditions: UDI reset command input (see section 22.4.3, UDI Reset)  Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000. Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to 1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip peripheral modules are initialized. See the register descriptions in the relevant sections for details. Table 4.
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• TLB invalid exception  Conditions: Comparison of TLB addresses shows address match but the TLB entry valid bit (V) is 0.  Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31–10). The ASID of PTEH indicates the ASID at the time the exception occurred. The way that generated the exception is set in the RC bits in MMUCR.
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• CPU address error  Conditions: a. Instruction fetch from odd address (4n + 1, 4n + 3) b. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) c. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) d. Virtual space accessed in user mode in the area H'80000000 to H'FFFFFFFF  Operations: The virtual address (32 bits) that caused the exception is set in TEA.
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• Illegal slot instruction  Conditions: a. When undefined code in a delay slot is decoded Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S b. When an instruction that rewrites PC in a delay slot is decoded Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR c.
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4.5.3 Interrupts 1. NMI — Conditions: NMI pin edge detection — Operations: PC after the instruction that receives the interrupt is saved to SPC, and SR at the point the interrupt is accepted is saved to SSR. H'01C0 is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR are set to 1 and a branch occurs to PC = VBR + H'0600. This interrupt is not masked by SR.IMASK and is accepted with top priority when the BL bit in SR is 0. When the BL bit is 1, the interrupt is masked.
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5. On-Chip Peripheral Interrupts — Conditions: The interrupt mask bits in SR are lower than the on-chip module (TMU, RTC, SCI, IrDA, SCIF, A/D, DMAC, WDT, REF) interrupt level and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. — Operations: The PC value after the instruction at which the interrupt is accepted is saved to SPC. SR at the point the interrupt is accepted is saved to SSR. The code corresponding to the interrupt source is set in INTEVT and INTEVT2.
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• SPC when exception occurs: The PC saved to SPC when an exception occurs is as shown below:  Re-executing-type exceptions: PC of the instruction that caused the exception is set in SPC and re-executed after return from exception handling. If the exception occurred in a delay slot, however, PC of the immediately prior delayed branch instruction is set in SPC. If the condition of the conditional delayed branch instruction is not satisfied, the delay slot PC is set in SPC.
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Rev. 5.
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Section 5 Cache 5.1 Overview 5.1.1 Features The cache specifications are listed in table 5.1. Table 5.1 Cache Specifications Parameter Specification Capacity 16 kbytes Structure Instruction/data mixed, 4-way set associative Locking Way 2 and way 3 are lockable Line size 16 bytes Number of entries 256 entries/way Write system P0, P1, P3, U0: Write-back/write-through selectable Replacement method Least-recently-used (LRU) algorithm 5.1.
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Address array (ways 0−3) Entry 0 V U Tag address Entry 1 Data array (ways 0−3) 0 LW0 LW1 LW2 LW3 LRU 0 1 1 . . . . . . . . . . . . . . . . . . Entry 255 255 255 24 (1 + 1 + 22) bits 128 (32 × 4) bits 6 bits LW0−LW3: Longword data 0−3 Figure 5.1 Cache Structure Address Array: The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data is not valid. The U bit indicates whether the entry has been written to in writeback mode.
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The LRU bits are initialized to 000000 by a power-on reset, but are not initialized by a manual reset. Table 5.2 LRU and Way Replacement (When the cache lock function is not used) LRU (5–0) Way to be Replaced 000000, 000100, 010100, 100000, 110000, 110100 3 000001, 000011, 001011, 100001, 101001, 101011 2 000110, 000111, 001111, 010110, 011110, 011111 1 111000, 111001, 111011, 111100, 111110, 111111 0 5.1.3 Register Configuration Table 5.3 shows details of the cache control register. Table 5.
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31 … … … … … … … … 6 5 4 3 2 1 0 CF CB WT CE : Reserved bits. Always 0 when reading. Data written here is also always 0. CF: Cache flush bit. Writing 1 flushes all cache entries (clears the V, U, and LRU bits of all cache entries to 0). Always reads 0. Write-back to external memory is not performed when the cache is flushed. CB: Write-back/write-through switchover bit. Indicates the cache’s operating mode for area P1. 1 = write-back mode, 0 = write-through mode.
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31 9 8 7 W3 W3 LOAD LOCK 2 1 0 W2 W2 LOAD LOCK W2LOCK: Way 2 lock bit. W2LOAD: Way 2 load bit. When W2LOCK = 1 & W2LOAD = 1 & SR, CL = 1, the prefetched data will always be loaded into Way2. In all other conditions the prefetched data will be loaded into the way pointed by LRU. W3LOCK: Way 3 lock bit. W3LOAD: Way 3 load bit. When W3LOCK = 1 & W3LOAD = 1 & SR, CL = 1, the prefetched data will always be loaded into Way3.
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Table 5.5 Way Replacement when Instructions Except for PREF Instruction Ended Up in a Cache Miss DSP bit W3LOAD W3LOCK W2LOAD W2LOCK Way to be replaced 0 * * * * Depends on LRU (table 5.2) 1 * 0 * 0 Depends on LRU (table 5.2) 1 * 0 * 1 Depends on LRU (table 5.6) 1 * 1 * 0 Depends on LRU (table 5.7) 1 * 1 * 1 Depends on LRU (table 5.8) *: Don't care Do not set as W3LOAD=1 and also W2LOAD=1 Table 5.
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5.3 Cache Operation 5.3.1 Searching the Cache If the cache is enabled, whenever instructions or data in memory are accessed the cache will be searched to see if the desired instruction or data is in the cache. Figure 5.4 illustrates the method by which the cache is searched. The cache is a physical cache and holds physical addresses in its address section. Entries are selected using bits 11–4 of the address (virtual) of the access to memory and the address tag of that entry is read.
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Virtual address 31 12 11 4 3 21 0 Entry selection Longword (LW) selection Ways 0−3 Ways 0−3 0 MMU V U Tag address LW0 LW1 LW2 1 255 Physical address CMP0 CMP1 CMP2 CMP3 Hit signal 1 CMP0: Comparison circuit 0 CMP1: Comparison circuit 1 CMP2: Comparison circuit 2 CMP3: Comparison circuit 3 Figure 5.4 Cache Search Scheme (Normal Mode) Rev. 5.
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5.3.2 Read Access Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The transfer unit is 32 bits. The LRU is updated. Read Miss: An external bus cycle starts and the entry is updated. The way replaced is the one least recently used. Entries are updated in 16-byte units. When the desired instruction or data that caused the miss is loaded from external memory to the cache, the instruction or data is transferred to the CPU in parallel with being loaded to the cache.
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PA (31−4) Longword 0 Longword 1 Longword 2 Longword 3 PA (31−4): Physical address written to external memory Longword 0−3: The line of cache data to be written to external memory Figure 5.5 Write-Back Buffer Configuration 5.3.6 Coherency of Cache and External Memory Use software to ensure coherency between the cache and the external memory.
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The following three operations on the address array are possible. (1) Address Array Read Reads the tag address, LRU, U bit, and V bit from the entry that corresponds to the entry address and w`ay that were specified in the address field. No associative operation will be performed, regardless of the value of the associative bit (the A bit).
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The following two operations on the data array are possible. Note that these operations will not change the information in the address array. (1) Data Array Read Reads the data at the position selected by the L bits (3-2) of the address field from the entry that corresponds to the entry address and way that were specified in the address field.
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5.4.3 Examples of Usage (1) Invalidating a Specific Entry A specific cache entry can be invalidated by accessing the allocated memory cache and writing a 0 to the entry’s U and V bits. The A bit is cleared to 0, and an address is specified for the entry address and the way. If the U bit of the way of the entry in question was set to 1, the entry is written back and the V and U bits specified by the write data are written to.
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In the following example, an address (32-bit) to be purged is specified in R0. MOV.L #H'00000FF0, R1 ; AND ; The entry address is fetched. R0, R1 MOV.L #H'F0000008, R2 ; OR ; The start is set to H'F0 and the A bit R1, R2 to 1. MOV.L #H'1FFFFC00, R3 ; AND ; The tag address is fetched. U = V = 0. R0, R3 MOV.L R3, @R2 ; Associative purge. The above operation should be performed using a non-cacheable area.
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Section 6 Interrupt Controller (INTC) 6.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority. 6.1.
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6.1.2 Block Diagram Figure 6.1 shows a block diagram of the INTC.
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6.1.3 Pin Configuration Table 6.1 shows the INTC pin configuration. Table 6.1 INTC Pins Name Abbreviation I/O Description Nonmaskable interrupt input pin NMI I Input of interrupt request signal, not maskable by the interrupt mask bits in SR. Interrupt input pins IRQ5–IRQ0 IRL3–IRL0 I Input of interrupt request signals, maskable by the interrupt mask bits in SR.
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6.1.4 Register Configuration The INTC has the 12 registers listed in table 6.2. Table 6.2 INTC Registers Name Abbr.
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6.2 Interrupt Sources There are five types of interrupt sources: NMI, IRQ, IRL,PINT, and on-chip peripheral modules. Each interrupt has a priority level (0–16), with 0 the lowest and 16 the highest. Priority level 0 masks an interrupt. 6.2.1 NMI Interrupt The NMI interrupt has the highest priority level of 16. When the BLMSK bit in the interrupt control register (ICR1) is 1 or the BL bit in the status register (SR) is 0, NMI interrupts are accepted when the MAI bit in the ICR1 register is 0.
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Interrupts IRQ4–IRQ0 can wake the chip up from the standby state when the relevant interrupt level is higher than the setting of I3–I0 in the SR register (but only when the RTC 32-kHz oscillator is used). If the IRQ edge is input immediately before the CPU enters the standby mode (during the period between when the CPU executes a SLEEP instruction and when STATUS0 becomes high level), the interrupt may not be detected.
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IRL3–IIRL0/IIRLS3–IIRLS0 Pins and Interrupt Levels Table 6.
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6.2.4 PINT Interrupts PINT interrupts are input by level from pins PINT0–PINT15. The priority level can be set by interrupt priority register D (IPRD) in a range from 0 to 15, in groups of PINT0–PINT7 and PINT8–PINT15. The PINT0/1 interrupt level should be held until the interrupt is accepted and interrupt handling is started. Correct operation cannot be guaranteed if the level is not maintained. The interrupt mask bits (I3–I0) in the status register (SR) are not affected by PINT interrupt handling.
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6.2.6 Interrupt Exception Handling and Priority Tables 6.4 and 6.5 list the codes for the interrupt event registers (INTEVT and INTEVT2), and the order of interrupt priority. Each interrupt source is assigned a unique code. The start address of the interrupt service routine is common to each interrupt source. This is why, for instance, the value of INTEVT or INTEVT2 is used as offset at the start of the interrupt service routine and branched to in order to identify the interrupt source.
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Table 6.
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Interrupt Source INTEVT Code (INTEVT2 Code) Interrupt Priority IPR (Bit (Initial Value) Numbers) Priority within IPR Default Setting Unit Priority RTC ATI H'480 (H'480) 0–15 (0) High PRI H'4A0 (H'4A0) CUI H'4C0 (H'4C0) ERI H'4E0 (H'4E0) RXI H'500 (H'500) TXI H'520 (H'520) TEI H'540 (H'540) WDT ITI H'560 (H'560) 0–15 (0) IPRB (15–12) — REF RCMI H'580 (H'580) 0–15 (0) IPRB (11–8) ROVI H'5A0 (H'5A0) SCI IPRA (3–0) High Low 0–15 (0) IPRB (7–4) High Low High Low Low Note:
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Table 6.
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Interrupt Source SCIF ERI2 RXI2 Interrupt Priority IPR (Bit (Initial Value) Numbers) 1 H'200–3C0* (H'900) 0–15 (0) 1 H'200–3C0* (H'920) IPRE (7–4) Priority within IPR Default Setting Unit Priority High TXI2 ADI 1 H'200–3C0* (H'980) 0–15 (0) Low IPRE (3–0) — TMU0 TUNI0 H'400 (H'400) 0–15 (0) IPRA (15–12) — TMU1 TUNI1 H'420 (H'420) 0–15 (0) IPRA (11–8) — TMU2 TUNI2 H'440 (H'440) 0–15 (0) IPRA (7–4) TICPI2 H'460 (H'460) ATI H'480 (H'480) RTC SCI High 1 H'200–3C0* (H'940) 1 H'200–
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Table 6.6 Interrupt Levels and INTEVT Codes Interrupt level INTEVT Code 15 H'200 14 H'220 13 H'240 12 H'260 11 H'280 10 H'2A0 9 H'2C0 8 H'2E0 7 H'300 6 H'320 5 H'340 4 H'360 3 H'380 2 H'3A0 1 H'3C0 Rev. 5.
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6.3 INTC Registers 6.3.1 Interrupt Priority Registers A to E (IPRA–IPRE) Interrupt priority registers A to E (IPRA to IPRE) are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for on-chip peripheral module, IRQ, and PINT interrupts. These registers are initialized to H'0000 by a power-on reset or manual reset, but are not initialized in standby mode.
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6.3.2 Interrupt Control Register 0 (ICR0) ICR0 is a register that sets the input signal detection mode of external interrupt input pin NMI, and indicates the input signal level at the NMI pin. This register is initialized to H'0000 or H'8000 by a power-on reset or manual reset, but is not initialized in standby mode.
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6.3.3 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ0 to IRQ5 individually: rising edge, falling edge, or low level. This register is initialized to H'4000 by a power-on reset or manual reset, but is not initialized in standby mode.
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Bit 12—IIRLS Enable (IRLSEN): Enables pins IRLS3–IRLS0. This bit is valid only when the IRQLVL bit is 1. Bit 12: IRLSEN Description 0 Pins IRLS3–IRLS0 disabled 1 Pins IRLS3–IRLS0 enabled (Initial value) Bits 11 and 10—IRQ5 Sense Select (IRQ51S, IRQ50S): Select whether the interrupt signal to the IRQ5 pin is detected at the rising edge, at the falling edge, or at the low level.
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Bits 5 and 4—IRQ2 Sense Select (IRQ21S, IRQ20S): Select whether the interrupt signal to the IRQ2 pin is detected at the rising edge, at the falling edge, or at the low level.
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6.3.4 Interrupt Control Register 2 (ICR2) ICR2 is a 16-bit readable/writable register that sets the detection mode for external interrupt input pins PINT0 to PINT15. This register is initialized to H'0000 by a power-on reset or manual reset, but is not initialized in standby mode.
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6.3.5 PINT Interrupt Enable Register (PINTER) PINTER is a 16-bit readable/writable register that enables interrupt requests input to external interrupt input pins PINT0 to PINT15. This register is initialized to H'0000 by a power-on reset or manual reset, but is not initialized in standby mode.
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6.3.6 Interrupt Request Register 0 (IRR0) IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ0 to IRQ5 and PINT0 to PINT15. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode.
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Bit 4—IRQ4 Interrupt Request (IRQ4R): Indicates whether there is interrupt request input to the IRQ4 pin. When edge detection mode is set for IRQ4, an interrupt request is cleared by clearing the IRQ4R bit. Bit 4: IRQ4R Description 0 No interrupt request input to IRQ4 pin 1 Interrupt request input to IRQ4 pin (Initial value) Bit 3—IRQ3 Interrupt Request (IRQ3R): Indicates whether there is interrupt request input to the IRQ3 pin.
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6.3.7 Interrupt Request Register 1 (IRR1) IRR1 is an 8-bit read-only register that indicates whether DMAC or IrDA interrupt requests have been generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode.
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Bit 3—DEI3 Interrupt Request (DEI3R): Indicates whether a DEI3 (DMAC) interrupt request has been generated. Bit 3: DEI3R Description 0 DEI3 interrupt request not generated 1 DEI3 interrupt request generated (Initial value) Bit 2—DEI2 Interrupt Request (DEI2R): Indicates whether a DEI2 (DMAC) interrupt request has been generated.
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Bits 7 to 5—Reserved: These bits are always read as 0. The write value should always be 0. Bit 4—ADI Interrupt Request (ADIR): Indicates whether an ADI (ADC) interrupt request has been generated. Bit 4: ADIR Description 0 ADI interrupt request not generated 1 ADI interrupt request generated (Initial value) Bit 3—TXI2 Interrupt Request (TXI2R): Indicates whether a TXI2 (SCIF) interrupt request has been generated.
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6.4 INTC Operation 6.4.1 Interrupt Sequence The sequence of interrupt operations is described below. Figure 6.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent, following the priority levels set in interrupt priority registers A to E (IPRA to IPRE). Lower priority interrupts are held pending.
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Program execution state ICR1.MAI = 1? No No Interrupt generated? Yes NMI = low? Yes No Yes No ICR1.BLMSK = 1? No SR.
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6.4.2 Multiple Interrupts When handling multiple interrupts, an interrupt handler should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT and INTEVT2. The code in INTEVT and INTEVT2 can be used as a branch-offset for branching to the specific handler. 2. Clear the cause of the interrupt in each specific handler. 3. Save SSR and SPC to memory. 4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR. 5.
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Table 6.8 Interrupt Response Time Number of States Item NMI IRQ Time for priority decision and SR mask bit comparison 0.5 × Icyc 0.5 × Icyc + 0.5 × Bcyc + 1 × Bcyc + 0.5 × Pcyc + 4.5 × 4 Pcyc* PINT Peripheral Modules Notes 0.5 × Icyc 0.5 × Icyc + 3.5 × Pcyc + 1.5 × 5 Pcyc* 0.5 × Icyc 6 + 3 × Pcyc* Wait time until end of sequence being executed by CPU X (≥ 0) × Icyc X (≥ 0) × Icyc X (≥ 0) × Icyc X (≥ 0) × Icyc Interrupt exception handling is kept waiting until the executing instruction ends.
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Number of States Item NMI IRQ PINT Peripheral Modules Response Total time (5.5 + X) × Icyc + 0.5 × Bcyc + 0.5 × Pcyc (5.5 + X) × Icyc + 1 × Bcyc + 4.5 × 4 Pcyc* (5.5 + X) × Icyc + 3.5 × 5 Pcyc* (5.5 + X) × Icyc + 1.5 5 × Pcyc* Minimum 7.5 2 case* 16.5 12.5 Maximum 8.5 + S 3 case* 26.5 + S 18.5 + S Notes (5.5 + X) × Icyc 6 + 3 × Pcyc* 5 6 8.5* /11.5* At 60-MHz (CKIO = 30) operation: 0.13–0.28 µs 5 10.5 + S* At 60-MHz (CKIO 6 = 15) operation: 16.5 + S* 0.26–0.
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Interrupt acceptance Start of interrupt handling 0.5 × Icyc + 0.5 × Bcyc + 2 × Pcyc 5 × Icyc IRL Instruction (instruction replaced by interrupt exception handling) IF Overrun fetch First instruction of interrupt handler ID EX EX EX EX IF IF ID EX IF: Instruction fetch: Instruction is fetched from memory in which program is stored. ID: Instruction decode: Fetched instruction is decoded. EX: Instruction execution: Data operation and address calculation are performed. Figure 6.
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Section 7 User Break Controller 7.1 Overview The user break controller (UBC) provides functions that simplify program debugging. This function makes it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Break conditions that can be set in the UBC are instruction fetch or data read/write, data size, data content, address value, and stop timing during instruction fetches. 7.1.
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7.1.2 Block Diagram Figure 7.1 shows a block diagram of the UBC.
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7.1.3 Table 7.1 Register Configuration Register Configuration Name Abbr.
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7.2 Register Descriptions 7.2.1 Break Address Register A (BARA) BARA is a 32-bit read/write register. BARA specifies the address used as a break condition in channel A. A power-on reset initializes BARA to H'00000000.
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7.2.2 Break Address Mask Register A (BAMRA) BAMRA is a 32-bit read/write register. BAMRA specifies bits masked in the break address specified by BARA. A power-on reset initializes BAMRA to H'00000000.
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7.2.3 Break Bus Cycle Register A (BBRA) Break bus cycle register A (BBRA) is a 16-bit read/write register, which specifies (1) CPU cycle or DMAC cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of channel A. A power-on reset initializes BBRA to H'0000.
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Bits 3 and 2—Read/Write Select A (RWA1, RWA0): Selects the read cycle or write cycle as the bus cycle of the channel A break condition. Bit 3: RWA1 Bit 2: RWA0 Description 0 0 Condition comparison is not performed 1 The break condition is the read cycle 1 (Initial value) 0 The break condition is the write cycle 1 The break condition is the read cycle or write cycle Bits 1 and 0—Operand Size Select A (SZA1, SZA0): Selects the operand size of the bus cycle for the channel A break condition.
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7.2.4 Break Address Register B (BARB) BARB is a 32-bit read/write register. BARB specifies the address used as a break condition in channel B. A power-on reset initializes BARB to H'00000000.
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7.2.5 Break Address Mask Register B (BAMRB) BAMRB is a 32-bit read/write register. BAMRB specifies bits masked in the break address specified by BARB. A power-on reset initializes BAMRB to H'00000000.
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7.2.6 Break Data Register B (BDRB) BDRB is a 32-bit read/write register. A power-on reset initializes BDRB to H'00000000.
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7.2.7 Break Data Mask Register B (BDMRB) BDMRB is a 32-bit read/write register. BDMRB specifies bits masked in the break data specified by BDRB. A power-on reset initializes BDMRB to H'00000000.
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7.2.8 Break Bus Cycle Register B (BBRB) Break bus cycle register B (BBRB) is a 16-bit read/write register, which specifies, (1) CPU cycle or DMAC cycle, (2) instruction fetch or data access, (3) read/write, and (4) operand size in the break conditions of channel B. A power-on reset initializes BBRB to H'0000.
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Bits 3 and 2—Read/Write Select B (RWB1, RWB0): Select the read cycle or write cycle as the bus cycle of the channel B break condition. Bit 3: RWB1 Bit 2: RWB0 Description 0 0 Condition comparison is not performed 1 The break condition is the read cycle 1 (Initial value) 0 The break condition is the write cycle 1 The break condition is the read cycle or write cycle Bits 1 and 0—Operand Size Select B (SZB1, SZB0): Select the operand size of the bus cycle for the channel B break condition.
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7.2.9 Break Control Register (BRCR) BRCR sets the following conditions: 1. Channels A and B are used in two independent channels condition or under the sequential condition. 2. A break is set before or after instruction execution. 3. A break is set by the number of execution times. 4. Determine whether to include data bus on channel B in comparison conditions. 5. Enable PC trace. 6. Enable the ASID check.
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Bit 21—Break ASID Mask A (BASMA): Specifies whether the bits of the channel A break ASID7-ASID0 (BASA7 to BASA0) set in BASRA are masked or not. Bit 21: BASMA Description 0 All BASRA bits are included in break condition, ASID is checked (Initial value) 1 No BASRA bits are included in break condition, ASID is not checked Bit 20—Break ASID Mask B (BASMB): Specifies whether the bits of channel B break ASID7ASID0 (BASB7 to BASB0) set in BASRB are masked or not.
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Bit 13—DMAC Condition Match Flag A (SCMFDA): When the on-chip DMAC bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit.
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Bit 6—PC Break Select B (PCBB): Selects the break timing of the instruction fetch cycle for channel B as before or after instruction execution. Bit 6: PCBB Description 0 PC break of channel B is set before instruction execution 1 PC break of channel B is set after instruction execution (Initial value) Bits 5 and 4—Reserved: These bits are always read as 0. The write value should always be 0.
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7.2.10 Execution Times Break Register (BETR) When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 2 12 – 1 times. A power-on reset initializes BETR to H'0000. When a break condition is satisfied, it decreases the BETR. A break is issued when the break condition is satisfied after the BETR becomes H'0001. Bits 15-12 are always read as 0 and 0 should always be written in these bits.
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7.2.11 Branch Source Register (BRSR) BRSR is a 32-bit read register. BRSR stores the last fetched address before branch and the pointer (3 bits) which indicates the number of cycles from fetch to execution for the last executed instruction. BRSR has the flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0, when BRSR is read and also initialized by power-on resets or manual resets. Other bits are not initialized by reset.
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Bits 30 to 28—Instruction Decode Pointer (PID2 to PID0): PID is a 3-bit binary pointer (0–7). These bits indicate the instruction buffer number which stores the last executed instruction before branch. Bits 30 to 28: PID Description Even PID indicates the instruction buffer number. Odd PiD+2 indicates the instruction buffer number Bits 27 to 0—Branch Source Address (BSA27 to BSA0): These bits store the last fetched address before branch. 7.2.
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Bit 31—BRDR Valid Flag (DVF): Indicates whether a branch destination address is stored. When a branch destination address is fetched, this flag is set to 1. This flag is set to 0 in reading BRDR. Bit 31: DVF Description 0 The value of BRDR register is invalid 1 The value of BRDR register is valid Bits 30 to 28—Reserved: These bits are always read as 0. The write value should always be 0. Bits 27 to 0—Branch Destination Address (BDA27 to BDA0): These bits store the first fetched address after branch.
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7.3 Operation Description 7.3.1 Flow of the User Break Operation The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses and the corresponding ASIDs are loaded in the break address registers (BARA and BARB) and break ASID registers (BASRA and BASRB). The masked addresses are set in the break address mask registers (BAMRA and BAMRB). The break data is set in the break data register (BDRB).
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3. When the condition is specified to be occurred after execution, the instruction set with the break condition is executed and then the break is generated prior to the execution of the next instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions. When this kind of break is set for a delay branch instruction, the break is generated at the instruction that then first accepts the break. 4.
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7.3.4 Sequential Break 1. By specifying SEQ in BRCR is set to 1, the sequential break is issued when channel B break condition matches after channel A break condition matches. A user break is ignored even if channel B break condition matches before channel A break condition matches. When channels A and B condition match at the same time, the sequential break is not issued. 2.
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7.3.6 PC Trace 1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, repeat, and interrupt) is generated, the address from which the branch source address can be calculated and the branch destination address are stored in BRSR and BRDR, respectively. The branch address and the pointer, which corresponds to the branch, are included in BRSR. 2. The branch address before branch occurs can be calculated from the address and the pointer stored in BRSR.
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reaches the bottom of the queues. After switching the PCTE bit (in BRCR) off and on, the values in the queues are invalid. The read pointer stay at the position before PCTE is switched, but the trace pointer restart at the bottom of the queues. 7.3.7 Usage Examples Break Condition Specified to a CPU Instruction Fetch Cycle 1.
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2.
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4.
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6.
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Break Condition Specified to a DMAC Data Access Cycle 1.
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7.3.8 Notes 1. Only CPU can read/write UBC registers. 2. UBC cannot monitor CPU and DMAC access in the same channel. 3. Notes in specification of sequential break are described below: a. A condition match occurs when B-channel match occurs in a bus cycle after an A-channel match occurs in another bus cycle in sequential break setting. Therefore, no condition match occurs even if a bus cycle, in which an A-channel match and a channel B match occur simultaneously, is set. b.
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Rev. 5.
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Section 8 Power-Down Modes 8.1 Overview In the power-down modes, all CPU and some on-chip peripheral module functions are halted. This lowers power consumption. 8.1.1 Power-Down Modes The SH7709S has the following power-down modes and function: 1. Sleep mode 2. Standby mode 3. Module standby function (TMU, RTC, SCI, UBC, DMAC, DAC, ADC, SCIF, and IrDA onchip peripheral modules) 4. Hardware standby mode Table 8.
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Table 8.1 Power-Down Modes State Mode Transition Conditions CPU RegCPG CPU ister On-Chip Memory On-Chip Peripheral Modules Pins External Memory Canceling Procedure Held Run Refresh 1.
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8.1.2 Pin Configuration Table 8.2 lists the pins used for the power-down modes. Table 8.2 Pin Configuration Pin Name Abbreviation I/O Description Processing state 1 STATUS1 O Operating state of the processor.
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Bit 7—Standby (STBY): Specifies transition to standby mode. Bit 7: STBY Description 0 Executing SLEEP instruction puts chip into sleep mode 1 Executing SLEEP instruction puts chip into standby mode (Initial value) Bits 6, 5, and 3—Reserved: These bits are always read as 0. The write value should always be 0. Bit 4—Standby Crystal (STBXTL): Specifies halting or operating of the clock pulse generator in standby mode.
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Bit 0—Module Standby 0 (MSTP0): Specifies halting of the clock supply to the serial communication interface SCI (an on-chip peripheral module). When the MSTP0 bit is set to 1, the supply of the clock to the SCI is halted. Bit 0: MSTP0 Description 0 SCI operates 1 Clock supply to SCI is halted 8.2.2 (Initial value) Standby Control Register 2 (STBCR2) The standby control register 2 (STBCR2) is a readable/writable 8-bit register that sets the powerdown mode.
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Bit 4—Module Stop 7 (MSTP7): Specifies halting of the clock supply to the DMAC (an on-chip peripheral module). When the MSTP7 bit is set to 1, the supply of the clock to the DMAC is halted. Bit 4: MSTP7 Description 0 DMAC runs 1 Clock supply to DMAC halted (Initial value) Bit 3—Module Stop 6 (MSTP6): Specifies halting of the clock supply to the DAC (an on-chip peripheral module). When the MSTP6 bit is set to 1, the supply of the clock to the DAC is halted.
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8.3 Sleep Mode 8.3.1 Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to run in sleep mode and the clock continues to be output to the CKIO and CKIO2 pins. In sleep mode, the STATUS1 pin is set high and the STATUS0 pin low. 8.3.
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8.4 Standby Mode 8.4.1 Transition to Standby Mode To enter standby mode, set the STBY bit to 1 in STBCR, then execute the SLEEP instruction. The chip switches from the program execution state to standby mode. In standby mode, power consumption is greatly reduced by halting not only the CPU, but the clock and on-chip peripheral modules as well. The clock output from the CKIO and CKIO2 pins also halts. CPU and cache register contents are held, but some on-chip peripheral modules are initialized. Table 8.
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8.4.2 Canceling Standby Mode Standby mode is canceled by an interrupt (NMI, IRQ, IRL, PINT, or on-chip peripheral module) or a reset. Canceling with an Interrupt: The on-chip WDT can be used for hot starts. When the chip detects an NMI, IRL, IRQ, PINT*1, or on-chip peripheral module (except interval timer)*2 interrupt, the clock will be supplied to the entire chip and standby mode canceled after the time set in the WDT’s timer control/status register has elapsed. The STATUS1 and STATUS0 pins both go low.
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Canceling with a Reset: Standby mode is canceled by a reset (power-on or manual). Keep the RESET pin low until the clock oscillation settles. The internal clock will continue to be output to the CKIO and CKIO2 pins. 8.4.3 Clock Pause Function In standby mode, the clock input from the EXTAL pin or CKIO pin can be halted and the frequency can be changed. This function is used as follows: 1. Enter standby mode using the appropriate procedures. 2.
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8.5 Module Standby Function 8.5.1 Transition to Module Standby Function Setting the standby control register MSTP8–MSTP0 bits to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. This function can be used to reduce the power consumption in normal mode and sleep mode. The module standby function holds the state prior to halting the external pins of the on-chip peripheral modules. TMU external pins hold their state prior to the halt. SCI external pins go to the reset state.
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8.6 Timing of STATUS Pin Changes The timing of STATUS1 and STATUS0 pin changes is shown in figures 8.1 to 8.8. 8.6.1 Timing for Resets Power-On Reset CKIO, CKIO2*4 PLL settling time RESETP STATUS Normal*2 Reset*1 Normal*2 RESETOUT 0 to 5 Bcyc*3 Notes: 1. 2. 3. 4. 0 to 30 Bcyc*3 Reset: HH (STATUS1 high, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle The CKIO2 output is available only in clock modes 0, 1, and 2. Figure 8.
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Manual Reset CKIO, CKIO2*5 RESETM STATUS Normal*3 Reset*2 Normal*3 RESETOUT 0 Bcyc or more*4 Notes: 1. 2. 3. 4. 5. 0 to 30 Bcyc*4 In a manual reset, STATUS becomes HH (reset) and the internal reset begins after waiting for the executing bus cycle to end. Reset: HH (STATUS1 high, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle The CKIO2 output is available only in clock modes 0, 1, and 2. Figure 8.3 Manual Reset STATUS Output Rev. 5.
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8.6.2 Timing for Canceling Standby Standby to Interrupt Oscillation stops Interrupt request WDT overflow CKIO, CKIO2*3 WDT count STATUS Normal*2 Standby*1 WAKEUP Notes: 1. 2. 3. Standby: LH (STATUS1 low, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) The CKIO2 output is available only in clock modes 0, 1, and 2. Figure 8.4 Standby to Interrupt STATUS Output Rev. 5.
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Standby to Power-On Reset Oscillation stops Reset CKIO, CKIO2*7 RESETP*1 STATUS Normal*5 Standby*4 *2 0 to 10 Bcyc*6 Notes: 1. 2. 3. 4. 5. 6. 7. Reset*3 Normal*5 0 to 30 Bcyc*6 When standby mode is cleared with a power-on reset, the WDT does not count. Keep RESETP low during the PLL’s oscillation settling time.
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Standby to Manual Reset Oscillation stops Reset CKIO, CKIO2*6 RESETM*1 Normal*4 STATUS Standby*3 Reset*2 Normal*4 0 to 20 Bcyc*5 Notes: 1. 2. 3. 4. 5. 6. When standby mode is cleared with a manual reset, the WDT does not count. Keep RESETM low during the PLL’s oscillation settling time. Reset: HH (STATUS1 high, STATUS0 high) Standby: LH (STATUS1 low, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle The CKIO2 output is available only in clock modes 0, 1, and 2. Figure 8.
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Sleep to Power-On Reset Reset CKIO, CKIO2*7 RESETP*1 STATUS Normal*5 Sleep*4 *2 0 to 10 Bcyc*6 Notes: 1. 2. 3. 4. 5. 6. 7. Reset*3 Normal*5 0 to 30 Bcyc*6 When the PLL1’s multiplication ratio is changed by a power-on reset, keep RESETP low during the PLL’s oscillation settling time. Undefined Reset: HH (STATUS1 high, STATUS0 high) Sleep: HL (STATUS1 high, STATUS0 low) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle The CKIO2 output is available only in clock modes 0, 1, and 2.
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Sleep to Manual Reset Reset CKIO, CKIO2*6 RESETM*1 STATUS Normal*4 Sleep*3 0 to 80 Bcyc*5 Notes: 1. 2. 3. 4. 5. 6. Reset*2 0 to 30 Bcyc*5 Keep RESETM low until STATUS becomes reset. Reset: HH (STATUS1 high, STATUS0 high) Sleep: HL (STATUS1 high, STATUS0 low) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle The CKIO2 output is available only in clock modes 0, 1, and 2. Figure 8.9 Sleep to Manual Reset STATUS Output Rev. 5.
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8.7 Hardware Standby Mode 8.7.1 Transition to Hardware Standby Mode Driving the CA pin low causes a transition to hardware standby mode. In hardware standby mode, all modules except those operating on an RTC clock are halted, as in the standby mode entered on execution of a SLEEP instruction ((software) standby mode). Hardware standby mode differs from (software) standby mode as follows. 1. Interrupts and manual resets are not accepted. 2. The TMU does not operate.
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8.7.3 Hardware Standby Mode Timing Figures 8.10 and 8.11 show examples of pin timing in hardware standby mode. The CA pin is sampled using EXTAL2 (32.768 kHz), and a hardware standby request is only recognized when the pin is low for two consecutive clock cycles. The CA pin must be held low while the chip is in hardware standby mode. Clock oscillation starts when the CA pin is driven high after the RESETP pin is driven low. Rcyc: EXTAL2 (32.
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CKIO, CKIO2*6 CA RESETP STATUS Standby Normal*3 WDT operation Standby*2 Undefined Reset*1 0−10 Bcyc*4 2 Rcyc or more*5 Notes: 1. 2. 3. 4. 5. 6. Reset: HH (STATUS1 high, STATUS0 high) Standby: LH (STATUS1 low, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle Rcyc: EXTAL2 (32.768 kHz) cycle The CKIO2 output is available only in clock modes 0, 1, and 2. Figure 8.11 Hardware Standby Mode Timing (When CA Goes Low during WDT Operation on Standby Mode Cancellation) Rev. 5.
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Rev. 5.
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Section 9 On-Chip Oscillation Circuits 9.1 Overview The on-chip oscillation circuits consist of a clock pulse generator (CPG) block and a watchdog timer (WDT) block. The WDT is a single-channel timer that counts the clock settling time and is used when clearing standby mode and temporary standbys, such as frequency changes. It can also be used as an ordinary watchdog timer or interval timer. 9.1.
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9.2 Overview of CPG 9.2.1 CPG Block Diagram A block diagram of the on-chip clock pulse generator is shown in figure 9.1.
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The clock pulse generator blocks function as follows: 1. PLL Circuit 1: PLL circuit 1 doubles, triples, quadruples, sextuples, or leaves unchanged the input clock frequency from the CKIO pin. The multiplication rate is set by the frequency control register. When this is done, the phase of the leading edge of the internal clock is controlled so that it will agree with the phase of the leading edge of the CKIO pin. 2.
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9.2.2 CPG Pin Configuration Table 9.1 lists the CPG pins and their functions. Table 9.1 CPG Pins and Functions Pin Name Symbol I/O Description Mode control pins MD0 I Set the clock operating mode MD1 I MD2 I Crystal I/O pins (clock input pins) XTAL O Connects a crystal oscillator EXTAL I Connects a crystal oscillator.
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9.3 Clock Operating Modes Table 9.3 shows the relationship between the mode control pin (MD2–MD0) combinations and the clock operating modes. Table 9.4 shows the usable frequency ranges in the clock operating modes. Table 9.
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Mode 7: In this mode, the CKIO pin is an input, an external clock is input to this pin, and undergoes waveform shaping, and also frequency multiplication according to the setting, by PLL circuit 1 before being supplied to the chip. In modes 0 to 2, the system clock is generated from the output of the chip’s CKIO pin. Consequently, if a large number of ICs are operating on the clock cycle, the CKIO pin load will be large. This mode, however, assumes a comparatively large-scale system.
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Clock Mode FRQCR PLL1 1, 2 7 PLL2 Clock Rate* Input Frequency (I:B:P) Range CKIO Frequency Range H'0100 ON (× 1) ON (× 4) 4:4:4 6.25 MHz to 8.34 MHz H'0101 ON (× 1) ON (× 4) 4:4:2 6.25 MHz to 16.67 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz H'0102 ON (× 1) ON (× 4) 4:4:1 6.25 MHz to 16.67 MHz 25 MHz to 66.67 MHz H'0111 ON (× 2) ON (× 4) 8:4:4 6.25 MHz to 8.34 MHz H'0112 ON (× 2) ON (× 4) 8:4:2 6.25 MHz to 16.67 MHz 25 MHz to 66.67 MHz H'0115 ON (× 2) ON (× 4) 4:4:4 6.25 MHz to 8.
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Cautions: 1. The frequency of the internal clock (Iφ) becomes: • The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 1. • Do not set the internal clock frequency lower than the CKIO pin frequency. 2. The frequency of the peripheral clock (Pφ) becomes: • The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 2.
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9.4 Register Descriptions 9.4.1 Frequency Control Register (FRQCR) The frequency control register (FRQCR) is a 16-bit readable/writable register used to specify the frequency multiplication ratio of PLL circuit 1 and the frequency division ratio of the internal clock and the peripheral clock. Only word access can be used on the FRQCR register. FRQCR is initialized to H'0102 by a power-on reset, but retains its value in a manual reset and in standby mode.
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Bits 14, 3, and 2—Internal Clock Frequency Division Ratio (IFC): These bits specify the frequency division ratio of the internal clock with respect to the output frequency of PLL circuit 1. Bit 14: IFC2 Bit 3: IFC1 Bit 2: IFC0 Description 0 0 0 ×1 0 0 1 × 1/2 1 0 0 × 1/3 0 1 0 × 1/4 Except above value (Initial value) Reserved (Setting prohibited) Note: Do not set the internal clock frequency lower than the CKIO pin frequency.
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9.5 Changing the Frequency The frequency of the internal clock and peripheral clock can be changed either by changing the multiplication ratio of PLL circuit 1 or by changing the division ratios of dividers 1 and 2. All of these are controlled by software through the frequency control register. The methods are described below. To the FRQCR register, do not set values other than those given in table 9.4. 9.5.
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9.6 Overview of WDT 9.6.1 Block Diagram of WDT Figure 9.2 shows a block diagram of the WDT. WDT Standby cancellation Standby mode Peripheral clock Standby control Internal reset request Divider Reset control Clock selection Clock selector Interrupt request Overflow Interrupt control Clock WTCSR WTCNT Bus interface Legend WTCSR: WTCNT: Watchdog timer control/status register Watchdog timer counter Figure 9.2 Block Diagram of WDT 9.6.
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9.7 WDT Registers 9.7.1 Watchdog Timer Counter (WTCNT) The watchdog timer counter (WTCNT) is an 8-bit readable/writable counter that increments on the selected clock. WTCNT differs from other registers in that it is more difficult to write to. See section 9.7.3, Notes on Register Access, for details. When an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time mode. Its address is H'FFFFFF84.
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Bit 6—Timer Mode Select (WT/IIT): Selects whether to use the WDT as a watchdog timer or an interval timer. Bit 6: WT/IIT Description 0 Used as interval timer 1 Used as watchdog timer (Initial value) Note: If WT/IT is modified when the WDT is running, the up-count may not be performed correctly. Bit 5—Reset Select (RSTS): Selects the type of reset when WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored.
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Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Division Ratio Overflow Period (when Pφ φ = 15 MHz) 0 0 0 1 17 µs 1 1/4 68 µs 0 1/16 273 µs 1 1/32 546 µs 0 1/64 1.09 ms 1 1/256 4.36 ms 1 1 0 1 (Initial value) 0 1/1024 17.48 ms 1 1/4096 69.91 ms Note: If bits CKS2–CKS0 are modified when the WDT is running, the up-count may not be performed correctly. Ensure that these bits are modified only when the WDT is not running. 9.7.
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9.8 Using the WDT 9.8.1 Canceling Standby The WDT can be used to cancel standby mode with an NMI or other interrupt. The procedure is described below. (The WDT does not run when a reset is used for canceling, so keep the RESET pin low until the clock stabilizes.) 1. Before transitioning to standby mode, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2.
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When the following three conditions are all met, FRQCR should not be changed while a DMAC transfer is in progress. • Bits IFC2 to IFC0 are changed. • STC2 to STC0 are not changed. • The clock ratio of Iφ (on-chip clock) to Bφ (bus clock) after the change is other than 1:1. 9.8.3 Using Watchdog Timer Mode 1. Set the WT/IT bit in the WTCSR register to 1, set the reset type in the RSTS bit, set the type of count clock in the CKS2–CKS0 bits, and set the initial value of the counter in the WTCNT counter.
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9.9 Notes on Board Design When Using an External Crystal Resonator: Place the crystal resonator, capacitors CL1 and CL2 close to the EXTAL and XTAL pins. To prevent induction from interfering with correct oscillation, use a common grounding point for the capacitors connected to the resonator, and do not locate a wiring pattern near these components.
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Avoid crossing signal lines VCC (PLL2) Power supply CAP2 VSS (PLL2) C2 VCC Reference values C1 = 470 pF C2 = 470 pF VCC (PLL1) VSS CAP1 C1 VSS (PLL1) Figure 9.5 Points for Attention when Using PLL Oscillator Circuit Rev. 5.
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Rev. 5.
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Section 10 Bus State Controller (BSC) 10.1 Overview The bus state controller (BSC) divides physical address space and output control signals for various types of memory and bus interface specifications. BSC functions enable the chip to link directly with synchronous DRAM, SRAM, ROM, and other memory storage devices without an external circuit. The BSC also allows direct connection to PCMCIA interfaces, simplifying system design and allowing high-speed data transfers in a compact system. 10.1.
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• Short refresh cycle control  The overflow interrupt function of the refresh counter enables the refresh function immediately after a self-refresh operation using low power-consumption DRAM • The refresh counter can be used as an interval timer  Outputs an interrupt request signal using the compare-match function  Outputs an interrupt request signal when the refresh counter overflows Rev. 5.
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10.1.2 Block Diagram Bus interface Wait controller WAIT Internal bus Figure 10.1 shows a block diagram of the bus state controller.
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10.1.3 Pin Configuration Table 10.1 shows the BSC pin configuration. Table 10.1 BSC Pins Pin Name Signal I/O Description Address bus A25–A0 O Address output Data bus D15–D0 I/O Data I/O D31–D16 I/O Data I/O when using 32-bit bus width Bus cycle start BS O Shows start of bus cycle. During burst transfers, asserted every data cycle. Chip select 0, 2–4 CS0, CS2–CS4 O Chip select signals to indicate area being accessed.
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Pin Name Signal I/O Description Data enable 3 WE3/DQMUU/ ICIOWR O When memory other than synchronous DRAM and PCMCIA is used, D31–D24 write strobe signal. When synchronous DRAM is used, selects D31– D24. When PCMCIA is used, strobe signal indicating I/O write. Read RD O Strobe signal indicating read cycle Wait WAIT I Wait state request signal Clock enable CKE O Clock enable control signal for synchronous DRAM IOIS16 IOIS16 I Signal indicating PCMCIA 16-bit I/O.
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10.1.4 Register Configuration The BSC has 21 registers (table 10.2). Synchronous DRAM also has a built-in synchronous DRAM mode register. These registers control direct connection interfaces to memory, wait states, and refreshes devices. Table 10.2 BSC Registers Name Abbr.
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10.1.5 Area Overview Space Allocation: In the architecture of the SH7709S, both logical spaces and physical spaces have 32-bit address spaces. The logical space is divided into five areas by the value of the upper bits of the address. The physical space is divided into eight areas. Logical space can be allocated to physical space using a memory management unit (MMU). For details, refer to section 3, Memory Management Unit (MMU), which describes area allocation for physical space. As shown in table 10.
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Table 10.
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Area 0: H'00000000 Area 1: H'04000000 Ordinary memory/ burst ROM Internal I/O Area 2: H'08000000 Ordinary memory/ synchronous DRAM Area 3: H'0C000000 Ordinary memory/ synchronous DRAM Area 4: H'10000000 Ordinary memory Area 5: H'14000000 Ordinary memory/ burst ROM/PCMCIA The PCMCIA interface is shared by the memory and I/O card Area 6: H'18000000 Ordinary memory/ burst ROM/PCMCIA The PCMCIA interface is shared by the memory and I/O card Figure 10.
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Shadow Space: Areas 0 and 2–6 are decoded by physical addresses A28–A26, which correspond to areas 000 to 110. Address bits 31–29 are ignored. This means that the range of area 0 addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the address space obtained by adding to it H'20000000 × n (n = 1–6). The address range for area 7, which is on-chip I/O space, is H'1C000000 to H'1FFFFFFF.
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Table 10.
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IC Memory Card Interface I/O Card Interface Pin Signal I/O Function Signal I/O Function SH7709S Pin 31 D1 I/O Data D1 I/O Data D1 32 D2 I/O Data D2 I/O Data D2 33 WP O Write protect IOIS16 O 16-bit I/O port IOIS16 34 GND Ground GND Ground — 35 GND Ground GND Ground — 36 CD1 O Card detection CD1 O Card detection — 37 D11 I/O Data D11 I/O Data D11 38 D12 I/O Data D12 I/O Data D12 39 D13 I/O Data D13 I/O Data D13 40 D14 I/O Data D14 I/O Data
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IC Memory Card Interface Pin Signal I/O Card Interface I/O Function Signal I/O Function SH7709S Pin — 61 REG I Attribute memory space select REG I Attribute memory space select 62 BVD2 O Battery voltage detection SPKR O Digital voice signal — 63 BVD1 O Battery voltage detection STSCHG O Card state change 64 D8 I/O Data D8 I/O Data D8 65 D9 I/O Data D9 I/O Data D9 66 D10 I/O Data D10 I/O Data D10 67 CD2 O Card detection CD2 O Card detection — 68 GND Grou
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Bit 15—Pin A25 to A0 Pull-Up (PULA): Specifies whether or not pins A25 to A0 are pulled up for 4 cycles immediately after BACK is asserted. Bit 15: PULA Description 0 Not pulled up 1 Pulled up (Initial value) Bit 14—Pin D31 to D0 Pull-Up (PULD): Specifies whether or not pins D31 to D0 are pulled up when not in use.
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Bits 10 and 9—Area 0 Burst ROM Control (A0BST1, A0BST0): Specify whether to use burst ROM in physical space area 0. When burst ROM is used, these bits set the number of burst transfers. Bit 10: A0BST1 Bit 9: A0BST0 Description 0 0 Access area 0 accessed as ordinary memory (Initial value) 1 Access area 0 accessed as burst ROM (4 consecutive accesses). Can be used when bus width is 8, 16, or 32. 0 Access area 0 accessed as burst ROM (8 consecutive accesses). Can be used when bus width is 8 or 16.
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Bit 6: A6BST1 Bit 5: A6BST0 Description 0 0 Access area 6 accessed as ordinary memory (initial value) 1 Burst access of area 6 (4 consecutive accesses). Can be used when bus width is 8, 16, or 32. 0 Burst access of area 6 (8 consecutive accesses). Can be used when bus width is 8 or 16. Should not be specified when bus width is 32. 1 Burst access of area 6 (16 consecutive accesses). Can be used only when bus width is 8. Should not be specified when bus width is 16 or 32.
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Bit 0—Area 6 Bus Type (A6PCM): Designates whether to access physical space area 6 as PCMCIA space. Bit 0: A6PCM Description 0 Physical space area 6 accessed as ordinary memory 1 Physical space area 6 accessed as PCMCIA space 10.2.2 (Initial value) Bus Control Register 2 (BCR2) Bus control register 2 (BCR2) is a 16-bit readable/writable register that selects the bus size of each area and whether an 8-bit port is used or not.
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Bit 2n + 1: AnSZ1 Bit 2n: AnSZ0 Port A / B Description 0 0 Not used Reserved (Setting prohibited) 1 0 Byte (8-bit) size 0 Word (16-bit) size 1 Longword (32-bit) size 0 1 10.2.3 1 Used Reserved (Setting prohibited) 1 Byte (8-bit) size 0 Word (16-bit) size 1 Reserved (Setting prohibited) Wait State Control Register 1 (WCR1) Wait state control register 1 (WCR1) is a 16-bit readable/writable register that specifies the number of idle (wait) state cycles inserted for each area.
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Bit 15—WAIT Sampling Timing Select (WAITSEL): Specifies the WAIT signal sampling timing. Bit 15: WAITSEL Description 0 Setting to 1 when using the WAIT signal* 1 Sampled WAIT signal at fall of CKIO (Initial value) Note: * Operation is not guaranteed if WAIT is asserted while WEITSEL = 0. Bits 14, 3, and 2 —Reserved: These bits are always read as 0. The write value should always be 0.
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Bits 15 to 13—Area 6 Wait Control (A6W2, A6W1, A6W0): Specify the number of wait states inserted in physical space area 6. Also specify the number of states for burst transfer.
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Bits 9 to 7—Area 4 Wait Control (A4W2, A4W1, A4W0): Specify the number of wait states inserted in physical space area 4. Description Bit 9: A4W2 Bit 8: A4W1 Bit 7: A4W0 Inserted Wait State WAIT Pin 0 0 0 0 Ignored 1 1 Enabled 0 2 Enabled 1 3 Enabled 0 4 Enabled 1 6 Enabled 0 8 Enabled 1 10 Enabled (Initial value) 1 1 0 1 Bits 6 and 5—Area 3 Wait Control (A3W1, A3W0): Specify the number of wait states inserted in physical space area 3.
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Bits 4 and 3—Area 2 Wait Control (A2W1, A2W0): Specify the number of wait states inserted in physical space area 2.
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10.2.5 Individual Memory Control Register (MCR) The individual memory control register (MCR) is a 16-bit readable/writable register that specifies RAS and CAS timing for synchronous DRAM (areas 2 and 3), specifies address multiplexing, and controls refresh. This enables direct connection of synchronous DRAM without external circuits. MCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
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Bits 13 and 12—RAS–CAS Delay (RCD1, RCD0): When synchronous DRAM interface is selected as connected memory, these bits set the bank active read/write command delay time. Bit 13: RCD1 Bit 12: RCD0 Description 0 0 1 cycle 1 2 cycles 0 3 cycles 1 4 cycles 1 (Initial value) Bits 11 and 10—Write-Precharge Delay (TRWL1, TRWL0): Set the synchronous DRAM write-precharge delay time. This designates the time between the end of a write cycle and the next bank-active command.
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Bits 6 to 3—Address Multiplex (AMX3, AMX2, AMX1, AMX0): Specify address multiplexing for synchronous DRAM. For Synchronous DRAM Interface: Bit6: AMX3 Bit5: AMX2 Bit 4: AMX1 Bit 3: AMX0 1 1 0 1 The row address begins with A10 (The A10 value is output at A1 when the row address is output. 4M × 16-bit × 4-bank products) 1 0 The row address begins with A11 (The A11 value is output at A1 when the row address is output.
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Bit 1—Refresh Mode (RMODE): Selects whether to perform an ordinary refresh or a selfrefresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 0, an auto-refresh is performed on synchronous DRAM at the period set by refresh-related registers RTCNT, RTCOR, and RTCSR. When a refresh request occurs during an external bus cycle, the refresh cycle is performed after the bus cycle ends.
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Bit 15—Area 6 Wait Control (A6W3): Specifies the number of inserted wait states for area 6 combined with bits A6W2–A6W0 in WCR2. Also specifies the number of transfer states in burst transfer. Clear this bit to 0 when area 6 is not set to PCMCIA.
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Bits 11, 7, and 6—Area 5 Address OE/W WE Assert Delay (A5TED2, A5TED1, A5TED0): Specify the delay time from address output to OE/WE assertion for the PCMCIA interface connected to area 5. Bit 11: A5TED2 Bit 7: A5TED1 Bit 6: A5TED0 Description 0 0 0 0.5-cycle delay 1 1.5-cycle delay 0 2.5-cycle delay 1 3.5-cycle delay 0 4.5-cycle delay 1 5.5-cycle delay 0 6.5-cycle delay 1 7.
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Bits 9, 3, and 2—Area 5 OE/W WE Negate Address Delay (A5TEH2, A5TEH1, A5TEH0): Specify the address hold delay time from OE/WE negation for the PCMCIA interface connected to area 5. Bit 9: A5TEH2 Bit 3: A5TEH1 Bit 2: A5TEH0 Description 0 0 0 0.5-cycle delay 1 1.5-cycle delay 0 2.5-cycle delay 1 3.5-cycle delay 0 4.5-cycle delay 1 5.5-cycle delay 0 6.5-cycle delay 1 7.
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10.2.7 Synchronous DRAM Mode Register (SDMR) The synchronous DRAM mode register (SDMR) is an 8-bit write-only register that is written to via the synchronous DRAM address bus. It sets synchronous DRAM mode for areas 2 and 3. SDMR must be set before accessing the synchronous DRAM. Writes to the synchronous DRAM mode register use the address bus rather than the data bus.
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10.2.8 Refresh Timer Control/Status Register (RTCSR) The refresh timer control/status register (RTCSR) is a 16-bit readable/writable register that specifies the refresh cycle, whether to generate an interrupt, and the cycle of that interrupt. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Make the RTCOR setting before setting bits CKS2 to CKS0 in RTCSR.
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Bits 5 to 3—Clock Select Bits (CKS2 to CKS0): Select the clock input to RTCNT. The source clock is the external bus clock (CKIO). The RTCNT count clock is CKIO divided by the specified ratio. RTCOR must be set before setting CKS2-CKS0.
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Bit 0—Refresh Count Overflow Limit Select (LMTS): Indicates the count limit value to be compared to the number of refreshes indicated in the refresh count register (RFCR). When the value in RFCR overflows the value specified by LMTS, the OVF flag is set. Bit 0: LMTS Description 0 Count limit value is 1024 1 Count limit value is 512 10.2.9 (Initial value) Refresh Timer Counter (RTCNT) RTCNT is a 16-bit register containing a readable/writable 8-bit counter that counts up on an input clock.
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10.2.10 Refresh Time Constant Register (RTCOR) The refresh time constant register (RTCOR) specifies the upper-limit value of RTCNT. The values of RTCOR and RTCNT (lower 8 bits) are constantly compared. When the values match, the compare match flag (CMF) in RTCSR is set and RTCNT is cleared to 0. When the refresh bit (RFSH) in the individual memory control register (MCR) is set to 1 and the refresh mode is set to auto refresh, a memory refresh cycle occurs when the CMF bit is set.
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Bit: 15 14 13 12 11 10 9 8 Initial value: 0 0 0 0 0 0 0 0 R/W: — — — — — — R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: 10.2.12 Cautions on Accessing Refresh Control Related Registers RFCR, RTCSR, RTCNT, and RTCOR require that a specific code be appended to the data when it is written to prevent data from being mistakenly overwritten by program overruns or other write operations (figure 10.5).
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10.2.13 MCS0 Control Register (MCSCR0) The MCS0 control register (MCSCR0) is a 16-bit readable/writable register that specifies the MCS[0] pin output conditions. MCSCR0 is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. As the MCS[0] pin is multiplexed as the PTC0 pin, when using the pin as MCS[0], bits PC0MD[1:0] in the PCCR register should be set to 00 (other function).
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10.2.14 MCS1 Control Register (MCSCR1) The MCS1 control register (MCSCR1) specifies the MCS[1] pin output conditions. The bit configuration and functions are the same as those of MCSCR0. 10.2.15 MCS2 Control Register (MCSCR2) The MCS2 control register (MCSCR2) specifies the MCS[2] pin output conditions. The bit configuration and functions are the same as those of MCSCR0. 10.2.16 MCS3 Control Register (MCSCR3) The MCS3 control register (MCSCR3) specifies the MCS[3] pin output conditions.
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10.3 BSC Operation 10.3.1 Endian/Access Size and Data Alignment The SH7709S supports both big endian, in which the 0 address is the most significant byte in the byte data, and little endian, in which the 0 address is the least significant byte. Switching between the two is designated by an external pin (MD5 pin) at the time of a power-on reset. After a poweron reset, big endian is engaged when MD5 is low; little endian is engaged when MD5 is high.
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Table 10.
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Table 10.
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Table 10.
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Table 10.
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10.3.2 Description of Areas Area 0: Area 0 physical address bits A28–A26 are 000. Address bits A31–A29 are ignored and the address range is H'00000000 + H'20000000 × n – H'03FFFFFF + H'20000000 × n (n = 0–6 and n = 1–6 are the shadow spaces). Ordinary memories such as SRAM, ROM, and burst ROM can be connected to this space. Byte, word, or longword can be selected as the bus width using external pins MD3 and MD4. When the area 0 space is accessed, the CS0 signal is asserted.
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Area 3: Area 3 physical address bits A28–A26 are 011. Address bits A31–A29 are ignored and the address range is H'0C000000 + H'20000000 × n – H'0FFFFFFF + H'20000000 × n (n = 0–6 and n = 1–6 are the shadow spaces). Ordinary memories such as SRAM and ROM, as well as synchronous DRAM, can be connected to this space. Byte, word or longword can be selected as the bus width using bits A3SZ1 and A3SZ0 bits in BCR2 for ordinary memory. When area 3 space is accessed, CS3 is asserted.
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When the area 5 space is accessed and ordinary memory is connected, the CS5 signal is asserted. The RD signal that can be used as OE and the WE0–WE3 signals for write control are also asserted. When the PCMCIA interface is used, the CE1A signal, CE2A signal, RD signal as OE signal, and WE1 signal are asserted. The number of bus cycles is selected between 0 and 10 wait cycles using the A5W2–A5W0 bits in WCR2.
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10.3.3 Basic Interface Basic Timing: The basic interface of the SH7709S uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. Figure 10.6 shows the basic timing of normal space accesses. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle. The CSn signal is negated on the T2 clock falling edge to secure the negation period.
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T1 T2 CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 BS Figure 10.6 Basic Timing of Basic Interface Rev. 5.
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Figures 10.7, 10.8, and 10.9 show examples of connection to 32, 16, and 8-bit data-width static RAM, respectively. 128k × 8-bit SRAM •••• A0 CS OE I/O7 •••• I/O0 WE •••• •••• •••• •••• A16 A0 CS OE I/O7 •••• •••• D8 WE1 D7 •••• •••• D16 WE2 D15 •••• •••• D24 WE3 D23 I/O0 WE •••• D0 WE0 A16 •••• •••• A2 CSn RD D31 A16 •••• •••• •••• A18 •••• SH7709S •••• A0 CS OE I/O7 •••• A16 A0 CS OE I/O7 •••• •••• •••• I/O0 WE I/O0 WE Figure 10.
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128k × 8-bit SRAM •••• A0 CS OE I/O7 •••• I/O0 WE •••• •••• •••• D0 WE0 A16 •••• •••• D8 WE1 D7 A0 CS OE I/O7 •••• •••• A1 CSn RD D15 A16 •••• •••• •••• A17 •••• SH7709S I/O0 WE Figure 10.8 Example of 16-Bit Data-Width Static RAM Connection Rev. 5.
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128k × 8-bit SRAM D0 WE0 •••• •••• A16 A0 CS OE I/O7 •••• •••• •••• A0 CSn RD D7 •••• •••• A16 •••• SH7709S I/O0 WE Figure 10.9 Example of 8-Bit Data-Width Static RAM Connection Rev. 5.
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Wait State Control: Wait state insertion on the basic interface can be controlled by the WCR2 settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification. For details, see section 10.2.4, Wait State Control Register 2 (WCR2). The specified number of Tw cycles are inserted as wait cycles using the basic interface wait timing shown in figure 10.10.
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When software wait insertion is specified by WCR2, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 10.11. A 2-cycle wait is specified as a software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore, if the WAIT signal has no effect if asserted in the T 1 cycle or the first Tw cycle. When the WAITSEL bit in the WCR1 register is set to 1, the WAIT signal is sampled at the falling edge of the clock.
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Wait states inserted by WAIT signal T1 Tw Tw Tw T2 CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 WAIT BS Figure 10.11 Basic Interface Wait State Timing (Wait State Insertion by WAIT Signal WAITSEL = 1) Rev. 5.
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10.3.4 Synchronous DRAM Interface Synchronous DRAM Direct Connection: Since synchronous DRAM can be selected by the CS signal, physical space areas 2 and 3 can be connected using RAS and other control signals in common. If the memory type bits (DRAMTP2–0) in BCR1 are set to 010, area 2 is ordinary memory space and area 3 is synchronous DRAM space; if set to 011, areas 2 and 3 are both synchronous DRAM space. Note, however, that synchronous DRAM must not be accessed when clock ratio Iφ:Bφ = 1:1.
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64M synchronous DRAM (1M × 16-bit × 4-bank) SH7709S DQ0 DQMU DQML Note : "x" is U or L •••• •••• A13 •••• A0 CLK CKE CS RAS CAS WE DQ15 •••• •••• •••• D16 DQMUU DQMUL D15 D0 DQMLU DQMLL •••• •••• A0 CLK CKE CS RAS CAS WE DQ15 •••• •••• A2 CKI0 CKE CSn RAS3x CASx RD/WR D31 •••• •••• A13 •••• •••• A15 DQ0 DQMU DQML Figure 10.12 Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width) Rev. 5.
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64M synchronous DRAM (1M × 16 bit × 4 bank) SH7709S ••• ••• D0 DQMLU DQMLL ••• ••• ••• ••• A0 CLK CKE CS RAS CAS WE DQ15 A1 CKIO CKE CSn RAS3x CASx RD/WR D15 ••• ••• A13 A12 A11 A14 A13 A12 DQ0 DQMU DQML Figure 10.13 Example of 64-Mbit Synchronous DRAM Connection (16-Bit Bus Width) Address Multiplexing: Synchronous DRAM can be connected without external multiplexing circuitry in accordance with the address multiplex specification bits AMX2-AMX0 in MCR. Table 10.
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Table 10.
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Setting External Address Pins Bus Memory AMX AMX AMX AMX Output Width Type 3 2 1 0 Timing 2M × 0 16bits × 4banks*2 1M × 0 16bits × 4banks*2 2M × 0 8bits × 4banks*2 1 1 1 0 0 0 1 0 1 A1 to A8 A9 A10 A11 A12 A13 A14 A15 A16 3 A10 L/H* A12 A22*4 A23*4 A24 Column address A1 to A9 A8 Row address A10 to A18 A19 A20 A21 A22*4 A23*4 A24 A17 Column address A1 to A9 A8 Row address A 9 to A17 A18 A19 A20 A21*4 A22*4 A23 A16 Column address A1 to A9 A8 Row address A10 to A18 A19 A20 A21 A22*4
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Table 10.
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independently for areas 2 and 3 by means of bits A2W1 and A2W0 or A3W1 and A3W0 in WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency cycles. Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 CKIO A25 to A16, A13 A12 A15, A14, A11 to A0 CS2 or CS3 RAS3x CASx RD/WR DQMxx D31 to D0 BS Figure 10.14 Basic Timing for Synchronous DRAM Burst Read Rev. 5.
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Figure 10.15 shows the burst read timing when RCD is set to 1, A3W1 and A3W0 are set to 10, and TPC is set to 1. The BS cycle, which is asserted for one cycle at the start of a bus cycle for normal access space, is asserted in each of cycles Td1–Td4 in a synchronous DRAM cycle. When a burst read is performed, the address is updated each time CAS is asserted.
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Single Read: Figure 10.16 shows the timing when a single address read is performed. As the burst length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is output. Consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed. Tr Tc1 Td1 Tpc CKIO A25 to A16, A13 A12 A15, A14, A11 to A0 CS2 or CS3 RAS3x CASx RD/WR DQMxx D31 to D0 BS Figure 10.16 Basic Timing for Synchronous DRAM Single Read Rev. 5.
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Burst Write: The timing chart for a burst write is shown in figure 10.17. In the SH7709S, a burst write occurs only in the event of cache write-back or 16-byte DMAC transfer. In a burst write operation, following the Tr cycle in which ACTV command output is performed, a WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and a WRITA command that performs autoprecharge is issued in the Tc4 cycle. In the write cycle, the write data is output at the same time as the write command.
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Tr Tc1 Tc2 Tc3 Tc4 (Trwl) (Tpc) CKIO Address upper bits A12, A11, A10 or A9 Address lower bits CSn RD/WR RAS3x CASx DQMxx D31 to D0 (read) BS Figure 10.17 Basic Timing for Synchronous DRAM Burst Write Rev. 5.
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Single Write: The basic timing chart for write access is shown in figure 10.18. In a single write operation, following the Tr cycle in which ACTV command output is performed, a WRITA command that performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write data is output at the same time as the write command.
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Tr Tc1 (Trwl) (Tpc) CKIO Address upper bits A12 or A10 Address lower bits CSn RD/WR RAS3x CASx DQMxx D31 to D0 BS CKE Figure 10.18 Basic Timing for Synchronous DRAM Single Write Rev. 5.
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Bank Active: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the RASD bit in MCR is 1, read/write command accesses are performed using commands without auto-precharge (READ, WRIT). In this case, precharging is not performed when the access ends.
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A Tnop cycle, in which no operation is performed, is inserted before the Tc cycle in which the READ command is issued in figure 10.20, but when synchronous DRAM is read, there is a twocycle latency for the DQMxx signal that performs the byte specification. If the Tc cycle were performed immediately, without inserting a Tnop cycle, it would not be possible to perform the DQMxx signal specification for Td1 cycle data output. This is the reason for inserting the Tnop cycle.
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Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 CKIO A25 to A16, A13 (A25 to A16, A11) A12 (A10) A15, A14, A11 to A0 (A15 to A12, A9 to A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31 to D0 BS Figure 10.19 Burst Read Timing (No Precharge) Rev. 5.
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Tnop Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 CKIO A25 to A16, A13 (A25 to A16, A11) A12 (A10) A15, A14, A11 to A0 (A15 to A12, A9 to A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31 to D0 BS Figure 10.20 Burst Read Timing (Same Row Address) Rev. 5.
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Tp Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 CKIO A25 to A16, A13 (A25 to A16, A11) A12 (A10) A15, A14, A11 to A0 (A15 to A12, A9 to A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31 to D0 BS Figure 10.21 Burst Read Timing (Different Row Addresses) Rev. 5.
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Tr Tc1 Tc2 Tc3 Tc4 CKIO A25 to A16, A13 (A25 to A16, A11) A12 (A10) A15, A14, A11 to A0 (A15 to A12, A9 to A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31 to D0 BS Figure 10.22 Burst Write Timing (No Precharge) Rev. 5.
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Tc1 Tc2 Tc3 Tc4 CKIO A25 to A16, A13 (A25 to A16, A11) A12 (A10) A15, A14, A11 to A0 (A15 to A12, A9 to A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31 to D0 BS Figure 10.23 Burst Write Timing (Same Row Address) Rev. 5.
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Tp Tr Tc1 Tc2 Tc3 Td4 CKIO A25 to A16, A13 (A25 to A16, A11) A12 (A10) A15, A14, A11 to A0 (A15 to A12, A9 to A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31 to D0 BS Figure 10.24 Burst Write Timing (Different Row Addresses) Rev. 5.
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Refreshing: The bus state controller is provided with a function for controlling synchronous DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1.
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RTCNT cleared to 0 when RTCNT = RTCOR RTCOR value RTCNT Time H'00000000 RTCSR.CKS(2 to 0) = 000 ≠ 000 CMF CMF flag cleared by start of refresh cycle External bus Auto-refresh cycle Figure 10.25 Auto-Refresh Operation Rev. 5.
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Tp TRr TRrw TRrw CKIO CKE CSn RAS3U, RAS3L CASU, CASL RD/WR Figure 10.26 Synchronous DRAM Auto-Refresh Timing Rev. 5.
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• Self-Refreshing Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit to 1. The self-refresh state is maintained while the CKE signal is low. Synchronous DRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0.
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Tp TRs1 (TRs2) (TRs2) TRs3 (Tpc) (Tpc) CKIO CKE CSn RAS3U, RAS3L CASU, CASL RD/WR Figure 10.27 Synchronous DRAM Self-Refresh Timing • Relationship between Refresh Requests and Bus Cycle Requests If a refresh request is generated during execution of a bus cycle, execution of the refresh is deferred until the bus cycle is completed. If a refresh request occurs when the bus has been released by the bus arbiter, refresh execution is deferred until the bus is acquired.
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Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed after powering on. To perform synchronous DRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the RAS, CAS, and RD/WR signals.
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Before mode register setting, a 100 µs idle time (depending on the memory manufacturer) must be guaranteed after powering on requested by the synchronous DRAM. If the reset signal pulse width is greater than this idle time, there is no problem in performing mode register setting immediately. The number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must be executed.
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10.3.5 Burst ROM Interface Setting bits A0BST1–0, A5BST1–0, and A6BST1–0 in BCR1 to a non-zero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed access to ROM that has a nibble access function. The timing for nibble access to burst ROM is shown in figure 10.29. Two wait cycles are set.
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T1 TW TW TB2 TB1 TW TB2 TB1 T2 CKIO A25 to A4 A3 to A0 CSn RD/WR RD D31 to D0 BS WAIT Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 10.29 Burst ROM Wait Access Timing Rev. 5.
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T1 TB2 TB1 TB2 TB1 TB2 TB1 CKIO A25 to A4 A3 to A0 CSn RD/WR RD D31 to D0 BS WAIT Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 10.30 Burst ROM Basic Access Timing Rev. 5.
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10.3.6 PCMCIA Interface In the SH7709S, setting the A5PCM bit in BCR1 to 1 makes the bus interface for physical space area 5 an IC memory card and I/O card interface as stipulated in JEIDA version 4.2 (PCMCIA2.1). Setting the A6PCM bit to 1 makes the bus interface for physical space area 6 an IC memory card and I/O card interface as stipulated in JEIDA version 4.2. When the PCMCIA interface is used, a bus size of 8 or 16 bits can be set by bits A5SZ1 and A5SZ0, or A6SZ1 and A6SZ0, in BCR2. Figure 10.
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A24 to A0 A25 to A0 D15 to D0 G D7 to D0 RD/WR CE1B/(CS6) CE1A/(CS5) CE2B CE2A D15 to D0 G DIR D15 to D8 PC card (memory/IO) G DIR SH7709S RD WE1 ICIORD ICIOWR CE1 CE2 OE WE/PGM (IORD) (IOWR) G WAIT WAIT IOIS16 (IOIS16) Card detection circuit Output port CD1, CD2 A25 to A0 G D7 to D0 D15 to D0 G DIR D15 to D8 PC card (memory/IO) G DIR CE1 CE2 OE WE/PGM G WAIT Card detection circuit Figure 10.31 Example of PCMCIA Interface Rev. 5.
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Memory Card Interface Basic Timing: Figure 10.32 shows the basic timing for the PCMCIA IC memory card interface. When physical space areas 5 and 6 are designated as PCMCIA interface areas, bus accesses are automatically performed as IC memory card interface accesses.
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Tpcm1 Tpcm2 CKIO A25 to A0 CExx RD/WR RD (read) D15 to D0 (read) WE (write) D15 to D0 (write) BS Figure 10.32 Basic Timing for PCMCIA Memory Card Interface Rev. 5.
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Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO A25 to A0 CExx RD/WR RD (read) D15 to D0 (read) WE (write) D15 to D0 (write) BS WAIT Figure 10.33 Wait Timing for PCMCIA Memory Card Interface Rev. 5.
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Memory Card Interface Burst Timing: In the SH7709S, when the IC memory card interface is selected, page mode burst access mode can be used, for read access only, by setting bits A5BST1 and A5BST0 in BCR1 for physical space area 5, or bits A6BST1 and A6BST0 in BCR1 for area 6. This burst access mode is not stipulated in JEIDA version 4.2 (PCMCIA2.1), but allows highspeed data access using ROM provided with a burst mode, etc. Burst access mode timing is shown in figures 10.34 and 10.35.
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Tpcm0 Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm2 Tpcm2w CKIO A25 to A4 A3 to A0 CExx RD/WR RD (read) D15 to D0 (read) BS WAIT Figure 10.35 Wait Timing for PCMCIA Memory Card Interface Burst Access Rev. 5.
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When the entire 32-Mbyte memory space is used as IC memory card interface space, the common memory/attribute memory switching signal REG is generated using a port, etc. If 16 Mbytes or less of memory space is sufficient, using 16 Mbytes of memory space as common memory space and 16 Mbytes as attribute memory space enables the A24 pin to be used for the REG signal.
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I/O Card Interface Timing: Figures 10.37 and 10.38 show the timing for the PCMCIA I/O card interface. Switching between the I/O card interface and the IC memory card interface is performed according to the accessed address. When PCMCIA is designed for physical space area 5, the bus access is automatically performed as an I/O card interface access when a physical address from H'16000000 to H'17FFFFFF is accessed.
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Tpci1 Tpci2 CKIO A25 to A0 CExx RD/WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) BS Figure 10.37 Basic Timing for PCMCIA I/O Card Interface Rev. 5.
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Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w CKIO A25 to A0 CExx RD/WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) BS WAIT IOIS16 Figure 10.38 Wait Timing for PCMCIA I/O Card Interface Rev. 5.
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Tpci0 Tpci1 Tpci1w Tpci2 Tpci1 Tpci1w Tpci2 Tpci2w CKIO A25 to A1 A0 CExx RD/WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) BS WAIT IOIS16 Figure 10.39 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Rev. 5.
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10.3.7 Waits between Access Cycles A problem associated with higher external memory bus operating frequencies is that data buffer turn-off on completion of a read from a low-speed device may be too slow, causing a collision with data in the next access. This results in lower reliability or incorrect operation. To avoid this problem, a data collision prevention feature has been provided. This memorizes the preceding access area and the kind of read/write.
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T1 T2 Twait T1 T2 Twait T1 T2 CKIO A25 to A0 CSm CSn BS RD/WR RD D31 to D0 Area m read Area n space read Area n space write Area m inter-access wait specification Area n inter-access wait specification Figure 10.40 Waits between Access Cycles 10.3.8 Bus Arbitration When a bus release request (BREQ) is asserted from an external device, buses are released after the bus cycle being executed is completed and a bus grant signal (BACK) is output.
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IRQOUT Pin Assertion Conditions: • When a memory refresh request has been generated but the refresh cycle has not yet begun • When an interrupt is generated with an interrupt request level higher than the setting of the interrupt mask bits (I3–I0) in the status register (SR). (This does not depend on the SR.BL bit.) 10.3.9 Bus Pull-Up With the SH7709S, address pin pull-up can be performed when the bus is released by setting the PULA bit in BCR1 to 1.
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CKIO D31 to D0 Pull-up Pull-up RD CSn Figure 10.42 Pull-Up Timing for Pins D31 to D0 (Read Cycle) CKIO D31 to D0 Pull-up Pull-up WEn CSn Figure 10.43 Pull-Up Timing for Pins D31 to D0 (Write Cycle) Rev. 5.
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10.3.10 MCS[0] to MCS[7] Pin Control The SH7709S is provided with pins MCS[0]–MCS[7] as dedicated CS pins for the ROM connected to area 0 or 2. Assertion of MCS[0]–MCS[7] is controlled by settings in MCSCR0– MCSCR7. This enables 32-, 64-, 128-, or 256-Mbit memory to be connected to area 0 or area 2. However, only CS2/0 = 0 (area 0) should be used for MCSCR0. Table 10.15 shows MCSCR0– MCSCR7 settings and MCS[0]–MCS[7] assertion conditions.
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Table 10.
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MCS[x] Assertion Conditions MCSCRx Settings CS2/0 CAP1 CAP0 A25 A24 A23 A22 CS0 CS2 Address Bus A[25:0] 1 — — — H L H'0000000 to H'1FFFFFF 256-Mbit ROM Notes 1 1 0 1 — — — H L H'2000000 to H'3FFFFFF 1 0 0 0 — — H L H'0000000 to H'0FFFFFF 128-Mbit ROM 0 1 — — H L H'1000000 to H'1FFFFFF 1 0 — — H L H'2000000 to H'2FFFFFF 1 1 — — H L H'3000000 to H'3FFFFFF 0 0 0 — H L H'0000000 to H'07FFFFF 64-Mbit ROM 0 0 1 — H L H'0800000 to H'0FFFFFF 0 1
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Rev. 5.
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Section 11 Direct Memory Access Controller (DMAC) 11.1 Overview The SH7709S includes a four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, memory-mapped external devices, and on-chip peripheral modules (IrDA, SCIF, A/D converter, and D/A converter). Using the DMAC reduces the burden on the CPU and increases overall operating efficiency.
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 Channel 3: In this channel, direct address mode or indirect address transfer mode can be specified. • Reload function: The value that was specified in the source address register can be automatically reloaded every four DMA transfers. This function is only available in channel 2. • Transfer requests  External request (From two DREQ pins (channels 0 and 1 only). DREQ can be detected either by the falling edge or by low level.
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11.1.2 Block Diagram Figure 11.1 shows a block diagram of the DMAC.
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11.1.3 Pin Configuration Table 11.1 shows the DMAC pins. Table 11.
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11.1.4 Register Configuration Table 11.2 summarizes the DMAC registers. The DMAC has a total of 17 registers: each channel has four registers, and one overall DMAC control register. Table 11.
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Channel Name Abbreviation R/W Initial Value Address Register Access Size Size 3 DMA source address register 3 SAR3 R/W Undefined H'04000050 (H'A4000050)*4 32 16, 32*2 DMA destination address register 3 DAR3 R/W Undefined H'04000054 (H'A4000054)*4 32 16, 32*2 DMA transfer count register 3 DMATCR3 R/W Undefined H'04000058 (H'A4000058)*4 24 16, 32*3 DMA channel control register 3 CHCR3 R/W*1 H'00000000 H'0400005C 32 (H'A400005C)*4 8, 16, 32*2 R/W*1 H'0000 H'04000060 (H'A4000060
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11.2 Register Descriptions 11.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) DMA source address registers 0–3 (SAR0–SAR3) are 32-bit readable/writable registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address. To transfer data in 16 bits or in 32 bits, specify a 16-bit or 32-bit address boundary address. When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the source address value.
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11.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit readable/writable registers that specify the destination address of a DMA transfer. These registers include a count function, and during a DMA transfer, these registers indicate the next destination address. To transfer data in 16-bit or 32-bit units, make sure to specify a destination address with a 16-byte boundary (16n address). An undefined value will be returned in a reset.
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11.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) DMA transfer count registers 0–3 (DMATCR0–DMATCR3) are 24-bit readable/writable registers that specify the DMA transfer count (bytes, words, or longwords). The number of transfers is 1 when the setting is H'000001, and 16,777,216 (the maximum) when H'000000 is set. During a DMA transfer, these registers indicate the remaining number of transfers. In 16-byte transfer, one 16-byte transfer (128 bits) is counted as one.
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11.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) DMA channel control registers 0–3 (CHCR0–CHCR3) are 32-bit readable/writable registers that specify the operation mode, transfer method, etc., for each channel. Bit 20 is only used in CHCR3; it is not used in CHCR0 to CHCR2. Consequently, writing to this bit is invalid in CHCR0 to CHCR2; 0 is read if this bit is read. Bit 19 is only used in CHCR2; it is not used in CHCR0, CHCR1, and CHCR3.
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Bits 31 to 21—Reserved: These bits are always read as 0. The write value should always be 0. Bit 20—Direct/Indirect Selection (DI): Selects direct address mode or indirect address mode in channel 3. This bit is only valid in CHCR3. Writing to this bit is invalid in CHCR0 to CHCR2; 0 is read if this bit is read. The write value should always be 0. When using 16-byte transfer, direct address mode must be specified. Operation is not guaranteed if indirect address mode is specified.
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Bit 17—Acknowledge Mode Bit (AM): Specifies whether DACK is output in the data read cycle or in the data write cycle in dual address mode. DACK is always output in single address mode, regardless of this bit specification. This bit is only valid in CHCR0 and CHCR1. Writing to this bit is invalid in CHCR2 and CHCR3; 0 is read if this bit is read. The write value should always be 0.
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Bits 13 and 12—Source Address Mode Bits 1 and 0 (SM1, SM0): Select whether the DMA source address is incremented, decremented, or left fixed.
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Bits 11 to 8—Resource Select Bits 3 to 0 (RS3 to RS0): Specify which transfer requests will be sent to the DMAC.
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Bit 6—D DREQ Select Bit (DS): Selects low-level or falling-edge detection as the sampling method for the DREQ pin used in external request mode. This bit is only valid in CHCR0 and CHCR1. Writing to this bit is invalid in CHCR2 and CHCR3; 0 is read if this bit is read. The write value should always be 0.
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Bit 1—Transfer End Bit (TE): Set to 1 on completion of the number of data transfers specified in DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated. If data transfer ends due to an NMI interrupt, a DMAC address error, or clearing of the DE bit or the DME bit in DMAOR before this bit is set to 1, this bit will not be set to 1. Even if the DE bit is set to 1 while this bit is set to 1, transfer is not enabled.
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11.2.5 DMA Operation Register (DMAOR) The DMA operation register (DMAOR) is a 16-bit readable/writable register that controls the DMAC transfer mode. These register values are initialized to 0 in a reset. The previous value is retained in standby mode.
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Bit 2—Address Error Flag Bit (AE): Indicates that an address error occurred by the DMAC. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to this bit. This bit can only be cleared by writing 0 after reading 1.
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11.3 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto-request, external request, and on-chip module request. The dual address mode has direct address transfer mode and indirect address transfer mode. Burst mode or cycle-steal mode can be selected as the bus mode. 11.3.
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Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1 and AE, NMIF, TE = 0? No Yes Transfer request?*1 No *2 *3 Yes Transfer (1 transfer unit); DMATCR − 1 → DMATCR, SAR and DAR updated DMATCR = 0? No Yes Bus mode, transfer request mode, DREQ detection selection system AE = 1 or NMIF = 1 or DE = 0 or DME = 0? No Yes DEI interrupt request (when IE = 1) Does AE = 1 or NMIF = 1 or DE = 0 or DME = 0? Yes Transfer end Transfer aborted No Normal end Notes: 1.
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11.3.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip module request. The request mode is selected in the RS3–RS0 bits of DMA channel control registers 0–3 (CHCR0–CHCR3).
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request signal. The source of the transfer request does not have to be the data transfer source or destination. When RXI is set as the transfer request, however, the transfer source must be the SCI's receive data register (RDR). Likewise, when TXI is set as the transfer request, the transfer source must be the SCI's transmit data register (TDR). If the transfer requester is the A/D converter, the data transfer source must be the A/D data register (ADDR). Table 11.
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11.3.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. Two modes (fixed mode and round-robin mode) are selected by priority bits PR1 and PR0 in the DMA operation register (DMAOR). Fixed Mode: In these modes, the priority order of the channels remain fixed.
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(1) When channel 0 transfers Initial priority order CH0 > CH1 > CH2 > CH3 Priority order after transfer Channel 0 becomes lowestpriority. CH1 > CH2 > CH3 > CH0 (2) When channel 1 transfers Initial priority order Priority order after transfer CH0 > CH1 > CH2 > CH3 Channel 1 becomes lowestpriority. The priority of channel 0, which was higher than channel 1, is also shifted. CH2 > CH3 > CH0 > CH1 (3) When channel 2 transfers Channel 2 becomes lowestpriority.
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Figure 11.4 shows how the priority order changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1. Transfer requests are generated simultaneously for channels 0 and 3. 2. Channel 0 has a higher priority than channel 3, so the channel 0 transfer begins first (channel 3 waits for transfer). 3.
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11.3.4 DMA Transfer Types The DMAC supports the transfers shown in table 11.5. Dual address mode has a direct address mode and indirect address mode. In direct address mode, an output address value is the data transfer target address; in indirect address mode, the value stored in the output address, not the output address value itself, is the data transfer target address. Data transfer timing depends on the bus mode, which may be cycle-steal mode or burst mode. Table 11.
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(1) In direct address transfer mode, DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. At this time, transfer data is temporarily stored in the DMAC. In the transfer between external memories as shown in figure 11.5, data is read to the DMAC from one external memory in a data read cycle, and then that data is written to the other external memory in a write cycle. Figure 11.
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CKIO A25 to A0 Transfer source address Transfer destination address CSn D31 to D0 RD WEn DACKn Data read cycle Data write cycle (1st cycle) (2nd cycle) Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn. Figure 11.
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D M A C DAR3 Temporary buffer Memory Data bus Address bus SAR3 Transfer source module Transfer destination module Data buffer When the value in SAR3 is an address, the memory data is read and the value is stored in the temporary buffer. The value to be read must be 32 bits since it is used for the address. If data bus connected to an external memory space is 16 bits wide, two bus cycles are necessary.
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CKIO A25 to A0 Transfer source address (H) Transfer source address (L) NOP Transfer destination address Indirect address CSn D31 to D0 Internal address bus Internal data bus Indirect address (H) Indirect address (L) Transfer source address *1 Transfer data Transfer data Indirect address NOP Transfer data Transfer source address *2 DMAC indirect address buffer Transfer data Indirect address DMAC data buffer Transfer data RD WEn Address read cycle (1st) (2nd) NOP cycle Data read cycl
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• Single Address Mode In single address mode, either the transfer source or transfer destination peripheral device is accessed (selected) by means of the DACK signal, and the other device is accessed by address. In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the external devices by outputting the DACK transfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer.
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CKIO Address output to external memory space A25 to A0 CSn WE Write strobe signal to external memory space D31 to D0 Data output from external device with DACK DACKn DACK signal (active-low) to external device with DACK BS (a) External device with DACK external memory space (ordinary memory) CKIO Address output to external memory space A25 to A0 CSn RD Read strobe signal to external memory space Data output from external memory space D31 to D0 DACKn DACK signal (active-low) to external device w
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CKIO A25 to A0 Transfer source address +4 +8 +12 CSn D31 to D0 RD WEn DACKn Figure 11.11 Example of DMA Transfer Timing in Single Address Mode (16-byte Transfer, External Memory Space (Ordinary Memory) → External Device with DACK) Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode in the TM bits of CHCR0–CHCR3. • Cycle-Steal Mode In cycle-steal mode, the bus is given to another bus master after a one-transfer-unit (byte, word, longword, or 16-byte unit) DMAC.
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DREQ Bus returned to CPU Bus cycle CPU CPU CPU DMAC DMAC Read CPU Write DMAC DMAC CPU Read CPU Write Figure 11.12 Example of DMA Transfer in Cycle-Steal Mode • Burst Mode Once the bus is obtained, the transfer is performed continuously until the transfer end condition is satisfied.
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Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 11.6 shows the relationship between request modes and bus modes by DMA transfer category. Table 11.
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Bus Mode and Channel Priority Order: When, for example, channel 1 is transferring in burst mode and there is a transfer request to channel 0, which has higher priority, the channel 0 transfer will begin immediately. At this time, if the priority is set in the fixed mode (CH0 > CH1), the channel 1 transfer will continue when the channel 0 transfer has completely finished, even if channel 0 is operating in cycle-steal mode or burst mode.
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11.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master. For details, see section 10, Bus State Controller (BSC). DREQ Pin Sampling Timing: In external request mode, the DREQ pin is sampled by clock pulse (CKIO) falling edge or low level detection.
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• Burst Mode, Level Detection In the case of burst mode with level detection, the DREQ sampling timing is the same as in cycle-steal mode. For example, in figure 11.20, DMAC transfer begins, at the earliest, three cycles after the first sampling is performed. The second sampling is started two cycles after the first. Subsequent sampling operations are performed in the idle cycle following the end of the DMA transfer cycle. In burst mode, also, the DACK output period is the same as in cycle-steal mode.
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DMAC(W) DMAC(R) CPU DMAC(R) DMAC(W) 3rd sampling DACK DRAK DREQ CKIO Bus cycle CPU 2nd sampling 1st sampling Figure 11.15 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles) Rev. 5.
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DMAC(R) CPU DMAC(R) DMAC(W) 3rd sampling DACK DRAK DREQ CKIO Bus cycle CPU 2nd sampling 1st sampling Figure 11.16 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles) Rev. 5.
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DMAC(W) CPU DMAC(R) DMAC(W) 3rd sampling 2nd sampling DACK (RD output) Bus cycle DRAK (High output) DREQ CKIO CPU 1st sampling Figure 11.17 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access: 4 Cycles) Rev. 5.
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Figure 11.18 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed) Rev. 5.
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Figure 11.19 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles) Rev. 5.00, 09/03, page 369 of 760 CPU DMAC(R) High High DMAC(W) 2nd sampling CPU DMAC(R) High 3rd sampling is performed, but since there is no DREQ falling edge, per-cycle sampling starts Note: When a DREQ falling edge is detected, DREQ must be high for at least one cycle before the sampling point.
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Figure 11.20 Burst Mode, Level Input Rev. 5.
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Figure 11.21 Burst Mode, Edge Input Rev. 5.
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11.3.6 Source Address Reload Function Channel 2 includes a reload function, in which the value is returned to the value set in the source address register (SAR2) every four transfers by setting the RO bit in CHCR2 to 1. 16-byte transfer cannot be used. Figure 11.22 shows this operation. Figure 11.
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CK Internal address bus Internal data bus SAR2 DAR2 SAR2+2 SAR2 data DAR2 SAR2+4 SAR2+2 data DAR2 SAR2+6 DAR2 SAR2+4 data SAR2 SAR2+6 data First transfer on channel 2 Second transfer Third transfer Fourth transfer SAR2 output DAR2 output SAR2+2 output DAR2 output SAR2+4 output DAR2 output SAR2+6 output DAR2 output Fifth transfer SAR2 reload SAR2 output DAR2 output Figure 11.
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11.3.7 DMA Transfer Ending Conditions The DMA transfer ending conditions are different for ending on an individual channel and ending on all channels together. At the end of transfer, the following conditions are applied except in the case where the value set in the DMA transfer count register (DMATCR) reaches 0. (a) Cycle-steal mode (external request, internal request, and auto-request) When the transfer ending conditions are satisfied, DMAC transfer request acceptance is suspended.
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Conditions for Ending on All Channels Simultaneously: Transfers on all channels end (1) when the AE or NMIF (NMI flag) bit is set to 1 in DMAOR, or (2) when the DME bit in DMAOR is cleared to 0. • Transfer ending when the NMIF bit is set to 1 in DMAOR: When an NMI interrupt occurs, the AE or NMIF bit is set to 1 in DMAOR and all channels stop their transfers according to the conditions in (a) to (d) described above, and pass the bus to an other bus master.
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11.4 Compare Match Timer (CMT) 11.4.1 Overview The DMAC has an on-chip compare match timer (CMT) to generate DMA transfer requests. The CMT has a 16-bit counter. Features The CMT has the following features: • Four types of counter input clock can be selected  One of four internal clocks (Pφ/4, Pφ/8, Pφ/16, Pφ/64) can be selected. • Generates a DMA transfer request when compare match occurs. Block Diagram Figure 11.24 shows a block diagram of the CMT.
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Register Configuration Table 11.7 summarizes the CMT register configuration. Table 11.
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Bit 0—Count Start 0 (STR0): Selects whether to operate or halt CMCNT0. Bit 0: STR0 Description 0 CMCNT0 count operation halted 1 CMCNT0 count operation (Initial value) Compare Match Timer Control/Status Register 0 (CMCSR0) The compare match timer control/status register 0 (CMCSR0) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the clock used for incrementation.
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Bit 6—Reserved: This bit can be read or written. The wite value should always be 0. Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): Select the clock input to CMCNT from among the four internal clocks obtained by dividing the system clock (Pφ). When the STR bit in CMSTR is set to 1, CMCNT0 begins incrementing on the clock selected by CKS1 and CKS0.
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Compare Match Constant Register 0 (CMCOR0) Compare match constant register 0 (CMCOR0) is a 16-bit register that sets the CMCNT0 compare match period. CMCOR0 is initialized to H'FFFF by a reset, but retains its previous value in standby mode. Bit: 15 14 13 12 11 10 9 8 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: R/W: 11.4.
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CMCNT0 Count Timing One of four clocks (Pφ/4, Pφ/8, Pφ/16, Pφ/64) obtained by dividing the Pφ clock can be selected with the CKS1 and CKS0 bits in CMCSR0. Figure 11.26 shows the timing. CK Internal clock CMCNT0 input clock CMCNT0 N-1 N N+1 Figure 11.26 Count Timing 11.4.4 Compare Match Compare Match Flag Setting Timing The CMF bit in the CMCSR0 register is set to 1 by the compare match signal generated when the CMCOR0 register and the CMCNT0 counter match.
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CK CMCNT0 input clock CMCNT0 N CMCOR0 N 0 Compare match signal CMF CMI Figure 11.27 CMF Setting Timing Compare Match Flag Clearing Timing The CMF bit in the CMCSR0 register is cleared by writing 0 to it after reading 1. Figure 11.28 shows the timing when the CMF bit is cleared by the CPU. CMCSR0 write cycle T1 T2 CK CMF Figure 11.28 Timing of CMF Clearing by the CPU Rev. 5.
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11.5 Examples of Use 11.5.1 Example of DMA Transfer between On-Chip IrDA and External Memory In this example, receive data of the on-chip IrDA is transferred to external memory using DMAC channel 3. Table 11.8 shows the transfer conditions and register settings. In addition, it is recommended that the trigger for the number of receive FIFO data bytes in IrDA be set to 1 (RTRG1 = RTRG0 = 0 in SCFCR). Table 11.
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11.5.2 Example of DMA Transfer between A/D Converter and External Memory In this example, DMA transfer is performed between the on-chip A/D converter (transfer source) and the external memory (transfer destination) with the address reload function on. Table 11.9 shows the transfer conditions and register settings. Table 11.
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As a result, the values in the DMAC are as shown in table 11.10 when the fourth transfer ends, depending on whether the address reload function is on or off. Table 11.
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Table 11.
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11.6 Usage Notes 1. The DMA channel control registers (CHCR0–CHCR3) can be accessed with any data size. The DMA operation register (DMAOR) must be accessed by byte (8 bits) or word (16 bits); other registers must be accessed by word (16 bits) or longword (32 bits). 2. Before rewriting the RS0–RS3 bits in CHCR0–CHCR3, first clear the DE bit to 0 (when rewriting CHCR with a byte address, be sure to set the DE bit to 0 in advance). 3.
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Rev. 5.
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Section 12 Timer (TMU) 12.1 Overview The SH7709S has a three-channel (channels 0 to 2) 32-bit timer unit (TMU). 12.1.1 Features The TMU has the following features: • Each channel is provided with an auto-reload 32-bit down counter. • Channel 2 is provided with an input capture function. • All channels are provided with 32-bit constant registers and 32-bit down counters that can be read or written to at any time.
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12.1.2 Block Diagram Pφ Bus interface Prescaler TOCR TCLK RTCCLK Clock controller TSTR Ch. 0 TCR0 Counter controller TCNT0 TCOR0 TUNI0 Ch. 1 TCR1 Counter controller Interrupt controller TUNI1 TCNT1 Module bus Interrupt controller TCOR1 Ch.
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12.1.3 Pin Configuration Table 12.1 shows the pin configuration of the TMU. Table 12.1 TMU Pin Channel Pin I/O Description Clock input/clock output TCLK I/O External clock input pin/input capture control input pin/realtime clock (RTC) output pin 12.1.4 Register Configuration Table 12.2 shows the TMU register configuration. Table 12.
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12.2 12.2.1 TMU Registers Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that selects whether to use the external TCLK pin as an external clock or an input capture control usage input pin, or an output pin for the on-chip RTC output clock. TOCR is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode.
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Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0. Bit 2—Counter Start 2 (STR2): Selects whether to run or halt timer counter 2 (TCNT2). Bit 2: STR2 Description 0 TCNT2 count halted 1 TCNT2 counts (Initial value) Bit 1—Counter Start 1 (STR1): Selects whether to run or halt timer counter 1 (TCNT1).
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Channels 0 and 1 TCR Bit Configuration: Bit: 15 14 13 12 11 10 9 8 — — — — — — — UNF Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bit: 7 6 5 4 3 2 1 0 — — UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W Channel 2 TCR Bit Configuration: Bit: 15 14 13 12 11 10 9 8 — — — — — — ICPF UNF Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W Bit: 7
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Bit 8—Underflow Flag (UNF): Status flag that indicates occurrence of a TCNT underflow. Bit 8: UNF Description 0 TCNT has not underflowed Clearing condition: When 0 is written to UNF 1 (Initial value) TCNT has underflowed Setting condition: When TCNT underflows* Note: * Contents do not change when 1 is written to UNF.
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Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): Select the external clock edge when the external clock is selected, or when the input capture function is used. Bit 4: CKEG1 Bit 3: CKEG0 Description 0 0 Count/capture register set on rising edge 1 Count/capture register set on falling edge X Count/capture register set on both rising and falling edge 1 (Initial value) Note: X means 0, 1, or ‘Don’t care’. Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): Select the TCNT count clock.
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12.2.4 Timer Constant Registers (TCOR) The TMU has three TCOR registers, one for each channel. TCOR specifies the value for setting in TCNT when a TCNT count-down results in an under flow. TCOR is a 32-bit readable/writable register. TCOR is initialized to H'FFFFFFFF by a power-on reset or manual reset, but is not initialized, and retains its contents, in standby mode.
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Because the internal bus for the SH7709S on-chip peripheral modules is 16 bits wide, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read. Since TCNT counts sequentially, this time lag can create discrepancies between the data in the upper and lower halves. To correct the discrepancy, a buffer register is connected to TCNT so that the upper and lower halves are not read separately. The entire 32-bit data in TCNT can thus be read at once.
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12.2.6 Input Capture Register (TCPR2) Input capture register 2 (TCPR2) is a read-only 32-bit register provided only in timer 2. Control of TCPR2 setting conditions due to the TCLK pin is affected by the input capture function bits (ICPE1/ICPE0 and CKEG1/CKEG0) in TCR2. When a TCPR2 setting indication due to the TCLK pin occurs, the value of TCNT2 is copied into TCPR2. TCNT2 is not initialized by a power-on reset or manual reset, but is not initialized, and retains its contents, or in standby mode.
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12.3 TMU Operation Each of three channels has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR). TCNT counts down. The auto-reload function enables cycle counting and counting by external events. Channel 2 has an input capture function. 12.3.1 General Operation When the STR0–STR2 bits in the timer start register (TSTR) are set to 1, the corresponding timer counter (TCNT) starts counting.
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Select operation Select counter clock (1) Set underflow interrupt generation (2) When using input capture function Set interrupt generation Set timer constant register (4) Initialize timer counter (5) Start counting (6) (3) Note: When an interrupt has been generated, clear the flag in the interrupt handler that caused it. If interrupts are enabled without clearing the flag, another interrupt will be generated. Figure 12.2 Setting the Count Operation Rev. 5.
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Auto-Reload Count Operation: Figure 12.3 shows the TCNT auto-reload operation. TCOR value set to TCNT during underflow TCNT value TCOR Time H'00000000 STR0−STR2 UNF Figure 12.3 Auto-Reload Count Operation TCNT Count Timing: • Internal Clock Operation: Set the TPSC2–TPSC0 bits in TCR to select whether peripheral module clock Pφ or one of the four internal clocks created by dividing it is used (Pφ/4, Pφ/16, Pφ/64, Pφ/256). Figure 12.4 shows the timing.
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• External Clock Operation: Set the TPSC2–TPSC0 bits in TCR to select the external clock (TCLK) as the timer clock. Use the CKEG1 and CKEG0 bits in TCR to select the detection edge. Rising, falling, or both edges may be selected. The pulse width of the external clock must be at least 1.5 peripheral module clock cycles for single edges or 2.5 peripheral module clock cycles for both edges. A shorter pulse width will result in accurate operation. Figure 12.5 shows the timing for both-edge detection.
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TCOR value set to TCNT during underflow TCNT value TCOR Time H'00000000 TCLK TCPR2 Set TCNT value ICPI Figure 12.7 Operation Timing when Using Input Capture Function (Using TCLK Rising Edge) 12.4 Interrupts There are two sources of TMU interrupts: underflow interrupts (TUNI) and interrupts when using the input capture function (TICPI2). 12.4.1 Status Flag Setting Timing UNF is set to 1 when the TCNT underflows. Figure 12.8 shows the timing.
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12.4.2 Status Flag Clearing Timing The status flag can be cleared by writing 0 from the CPU. Figure 12.9 shows the timing. TCR write cycle T1 T2 T3 Pφ Peripheral address bus TCR address UNF, ICPF Figure 12.9 Status Flag Clearing Timing 12.4.3 Interrupt Sources and Priorities The TMU produces underflow interrupts for each channel. When the interrupt request flag and interrupt enable bit are both set to 1, an interrupt is requested.
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12.5 Usage Notes 12.5.1 Writing to Registers Synchronization processing is not performed for timer counting during register writes. When writing to registers, always clear the appropriate start bits for the channel (STR2–STR0) in the timer start register (TSTR) to halt timer counting. 12.5.2 Reading Registers Synchronization processing is performed for timer counting during register reads.
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Section 13 Realtime Clock (RTC) 13.1 Overview The SH7709S has a realtime clock (RTC) with its own 32.768-kHz crystal oscillator. 13.1.
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13.1.2 Block Diagram Figure 13.1 shows a block diagram of the RTC. Oscillator circuit XTAL2 32.768 kHz 128 Hz 30second Reset ADJ R64CNT RSECCNT Prescaler (÷ 2) 16.
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13.1.3 Pin Configuration Table 13.1 shows the RTC pin configuration. Table 13.
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13.1.4 RTC Register Configuration Table 13.2 shows the RTC register configuration. Table 13.
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13.2 RTC Registers 13.2.1 64-Hz Counter (R64CNT) The 64-Hz counter (R64CNT) is an 8-bit read-only register that indicates the states of the RTC divider circuit, RTC prescaler, and R64CNT between 64 Hz and 1 Hz. R64CNT is initialized to H'00 by setting the RESET bit in RTC control register 2 (RCR2) or the ADJ bit in RCR2 to 1. R64CNT is not initialized by a power-on reset or manual reset, or in standby mode. Bit 7 is always read as 0. Bit: 13.2.
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13.2.3 Minute Counter (RMINCNT) The minute counter (RMINCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded minute section of the RTC. The count operation is performed by a carry for each minute of the second counter. The range that can be set is 00–59 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2.
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13.2.5 Day of Week Counter (RWKCNT) The day of week counter (RWKCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded day of week section of the RTC. The count operation is performed by a carry for each day of the date counter. The range that can be set is 0–6 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2.
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13.2.6 Date Counter (RDAYCNT) The date counter (RDAYCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded date section of the RTC. The count operation is performed by a carry for each day of the hour counter. The range that can be set is 01–31 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2.
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13.2.8 Year Counter (RYRCNT) The year counter (RYRCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded year section of the RTC. The least significant 2 digits of the western calendar year are displayed. The count operation is performed by a carry for each year of the month counter. The range that can be set is 00–99 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2.
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13.2.10 Minute Alarm Register (RMINAR) The minute alarm register (RMINAR) is an 8-bit readable/writable register, and an alarm register corresponding to the BCD-coded minute section counter RMINCNT of the RTC. When the ENB bit is set to 1, a comparison with the RMINCNT value is performed.
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13.2.12 Day of Week Alarm Register (RWKAR) The day of week alarm register (RWKAR) is an 8-bit readable/writable register, and an alarm register corresponding to the BCD-coded day of week section counter RWKCNT of the RTC. When the ENB bit is set to 1, a comparison with the RWKCNT value is performed.
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13.2.13 Date Alarm Register (RDAYAR) The date alarm register (RDAYAR) is an 8-bit readable/writable register, and an alarm register corresponding to the BCD-coded date section counter RDAYCNT of the RTC. When the ENB bit is set to 1, a comparison with the RDAYCNT value is performed.
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13.2.15 RTC Control Register 1 (RCR1) The RTC control register 1 (RCR1) is an 8-bit readable/writable register that affects carry flags and alarm flags. It also selects whether to generate interrupts for each flag. Because flags are sometimes set after an operand read, do not use this register in read-modify-write processing. RCR1 is initialized to H'00 by a power-on reset or a manual reset. In a manual reset, all bits are initialized to H'00 except for the CF flag, which is undefined.
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Bit 3—Alarm Interrupt Enable Flag (AIE): When the alarm flag (AF) is set to 1, the AIE bit allows interrupts. Bit 3: AIE Description 0 An alarm interrupt is not generated when the AF flag is set to 1 (Initial value) 1 An alarm interrupt is generated when the AF flag is set to 1 Bit 0—Alarm Flag (AF): The AF flag is set to 1 when the alarm time set in an alarm register (only registers with ENB bit set to 1) matches the clock and calendar time.
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Bits 6 to 4—Periodic Interrupt Flags (PES2-PES0): Specify the periodic interrupt.
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Bit 0—Start Bit (START): Halts and restarts the counter (clock). Bit 0: START Description 0 Second/minute/hour/day/week/month/year counter halts 1 Second/minute/hour/day/week/month/year counter runs normally (Initial value) Note: The 64-Hz counter always runs unless stopped with the RTCEN bit. 13.3 RTC Operation 13.3.1 Initial Settings of Registers after Power-On All the registers should be set after the power is turned on. 13.3.2 Setting the Time Figure 13.
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13.3.3 Reading the Time Figure 13.3 shows how to read the time. If a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. Part (a) in figure 13.3 shows the method of reading the time without using interrupts; part (b) in figure 13.3 shows the method using carry interrupts. To keep programming simple, method (a) should normally be used. a.
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13.3.4 Alarm Function Figure 13.4 shows how to use the alarm function. Alarms can be generated using seconds, minutes, hours, day of the week, date, month, or any combination of these. Set the ENB bit (bit 7) to 1 in the register to which the alarm applies, and then set the alarm time in the lower bits. Clear the ENB bit to 0 in registers to which the alarm does not apply. When the clock and alarm times match, 1 is set in the AF bit (bit 0) in RCR1.
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13.3.5 Crystal Oscillator Circuit Crystal oscillator circuit constants (recommended values) are shown in table 13.5, and the RTC crystal oscillator circuit in figure 13.5. Table 13.5 Recommended Oscillator Circuit Constants (Recommended Values) fosc Cin Cout 32.768 kHz 10 to 22 pF 10 to 22 pF Rf SH7709S RD XTAL2 EXTAL2 XTAL Cin Cout Notes: 1.
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13.4 Usage Notes 13.4.1 Register Writing during RTC Count The following RTC registers cannot be written to during an RTC count (while bit 0 = 1 in RCR2). RSECCNT, RMINCNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT, RYRCNT The RTC count must be halted before writing to any of the above registers. 13.4.2 Use of Realtime Clock (RTC) Periodic Interrupts The method of using the periodic interrupt function is shown in figure 13.6.
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Section 14 Serial Communication Interface (SCI) 14.1 Overview The SH7709S has an on-chip serial communication interface (SCI) that supports both asynchronous and clock synchronous serial communication. It also has a multiprocessor communication function for serial communication among two or more processors. The SCI supports a smart card interface, which is a serial communication feature for IC card interfaces that conforms to the ISO/IEC standard 7816-3 for identification cards.
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• Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external) • Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receiveerror interrupts are requested independently. • When the SCI is not in use, it can be stopped by halting the clock supplied to it, saving power. 14.1.2 Block Diagram Bus interface Figure 14.1 shows a block diagram of the SCI.
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Figures 14.2, 14.3, and 14.4 show block diagrams of the SCI I/O port pins. SCIF pin I/O and data control is performed by bits 11 to 8 of SCPCR and bits 5 and 4 of SCPDR. For details, see section 14.2.8, SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR).
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Reset R D SCP0MD0 Q C Internal data bus PCRW Reset R Q D SCP0MD1 C PCRW Reset SCPT[0]/TxD0 R Q D SCP0DT1 C SCI PDRW Output enable Serial transmission output Legend PCRW: SCPCR write PDRW: SCPDR write Figure 14.3 SCPT[0]/TxD0 Pin Rev. 5.
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SCI SCPT[0]/RxD0 Serial receive data Internal data bus PDRR* Legend PDRR: PDR read Note: * When reading the RxD0 pin, set the RE bit in SCSCR to 1. Figure 14.4 SCPT[0]/RxD0 Pin 14.1.3 Pin Configuration The SCI has the serial pins summarized in table 14.1. Table 14.
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14.1.4 Register Configuration Table 14.2 summarizes the SCI internal registers. These registers select the communication mode (asynchronous or synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. Table 14.
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14.2.2 Receive Data Register (SCRDR) The receive data register (SCRDR) stores serial receive data. The SCI completes the reception of one byte of serial data by moving the received data from the receive shift register (SCRSR) into SCRDR for storage. SCRSR is then ready to receive the next data. This double buffering allows the SCI to receive data continuously. The CPU can read but not write to SCRDR. SCRDR is initialized to H'00 by a reset and in standby or module standby mode.
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14.2.4 Transmit Data Register (SCTDR) The transmit data register (SCTDR) is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in SCTDR into SCTSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in SCTDR during serial transmission from SCTSR. The CPU can always read and write to SCTDR.
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Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data in asynchronous mode. In the synchronous mode, the data length is always eight bits, regardless of the CHR setting. Bit 6: CHR Description 0 8-bit data 7-bit data* 1 (Initial value) Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit data register (SCTDR) is not transmitted. Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode.
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Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in synchronous mode because no stop bits are added. When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character.
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14.2.6 Serial Control Register (SCSCR) The serial control register (SCSCR) operates the SCI transmitter/receiver, selects the serial clock output in asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. SCSCR is initialized to H'00 by a reset and in standby or module standby mode.
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Bit 5—Transmit Enable (TE): Enables or disables the SCI serial transmitter. Bit 5: TE Description 0 Transmitter disabled* 2 Transmitter enabled* 1 1 (Initial value) Notes: 1. The transmit data register empty bit (TDRE) in the serial status register (SCSSR) is fixed at 1. 2. Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status register (SCSSR) is cleared to 0 after writing of transmit data into the SCTDR.
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Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if SCTDR does not contain new transmit data when the MSB is transmitted.
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14.2.7 Serial Status Register (SCSSR) The serial status register (SCSSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate the SCI operating state. The CPU can always read and write to SCSSR, but cannot write 1 to the status flags (TDRE, RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written.
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Bit 6—Receive Data Register Full (RDRF): Indicates that SCRDR contains received data. Bit 6: RDRF Description 0 SCRDR does not contain valid receive data (Initial value) [Clearing conditions] (1) RDRF is cleared to 0 when the chip is reset or enters standby mode. (2) Software reads RDRF after it has been set to 1, then writes 0 in RDRF. 1 SCRDR contains valid receive data [Setting condition] RDRF is set to 1 when serial data is received normally and transferred from SCRSR to SCRDR.
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Bit 4—Framing Error (FER): Indicates that data reception aborted due to a framing error in asynchronous mode. Bit 4: FER Description 0 1 Receiving is in progress or has ended normally* (Initial value) [Clearing conditions] (1) FER is cleared to 0 when the chip is reset or enters standby mode. (2) When software reads FER after it has been set to 1, then writes 0 to FER.
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Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted, SCTDR did not contain valid data, so transmission has ended. TEND is a read-only bit and cannot be written to. Bit 2: TEND Description 0 Transmission is in progress [Clearing condition] TEND is cleared to 0 when software reads TDRE after it has been set to 1, then writes 0 to TDRE.
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14.2.8 SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR) The SC port control register (SCPCR) and SC port data register (SCPDR) control I/O and data for the port pins multiplexed with the serial communication interface (SCI) pins. SCPCR settings are used to perform I/O control, to enable data written in SCPDR to be output to the TxD pin, and input data to be read from the RxD pin, and to control serial transmission/reception breaks.
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SCPDR Bit 1—Serial Clock Port Data (SCP1DT): Specifies the serial port SCK pin I/O data. Input or output is specified by the SCP1MD1 and SCP1MD0 bits. In output mode, the value of the SCP1DT bit is output to the SCK pin. Bit 1: SCP1DT Description 0 I/O data is low 1 I/O data is high (Initial value) SCPCR Bits 1 and 0—Serial Port Break I/O (SCP0MD1, SCP0MD0): Specify the serial port TxD pin output condition.
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14.2.9 Bit Rate Register (SCBRR) The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a reset, and in module standby or standby mode. Each channel has independent baud rate generator control, so different values can be set in two channels.
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Table 14.4 lists examples of SCBRR settings in asynchronous mode, and table 14.5 lists examples of SCBRR settings in synchronous mode. Table 14.4 Bit Rates and SCBRR Settings in Asynchronous Mode Pφ φ (MHz) 2 2.097152 2.4576 Bit Rate (bits/s) n N Error (% %) n N Error (% %) n N Error (% %) 110 1 141 0.03 1 148 –0.04 1 174 –0.26 150 1 103 0.16 1 108 0.21 1 127 0.00 300 0 207 0.16 0 217 0.21 0 255 0.00 600 0 103 0.16 0 108 0.21 0 127 0.00 1200 0 51 0.
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Pφ φ (MHz) 4.9152 5 6 Bit Rate (bits/s) n N Error (% %) n N Error (% %) n N Error (% %) 110 2 86 0.31 2 88 –0.25 2 106 –0.44 150 1 255 0.00 2 64 0.16 2 77 0.16 300 1 127 0.00 1 129 0.16 1 155 0.16 600 0 255 0.00 1 64 0.16 1 77 0.16 1200 0 127 0.00 0 129 0.16 0 155 0.16 2400 0 63 0.00 0 64 0.16 0 77 0.16 4800 0 31 0.00 0 32 –1.36 0 38 0.16 9600 0 15 0.00 0 15 1.73 0 19 –2.34 19200 0 7 0.00 0 7 1.73 0 9 –2.
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Pφ φ (MHz) 14.7456 16 19.6608 20 Bit Rate (bits/s) n N Error (% %) n N Error (% %) n N Error (% %) n N Error (% %) 110 3 64 0.70 3 70 0.03 3 86 0.31 3 88 –0.25 150 2 191 0.00 2 207 0.16 2 255 0.00 3 64 0.16 300 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 600 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 1200 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 2400 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 4800 0 95 0.
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Table 14.5 Bit Rates and SCBRR Settings in Synchronous Mode Pφ φ (MHz) 4 8 16 28.7 30 Bit Rate (bits/s) n N n N n N n N n N 110 — — — — — — — — — — 250 2 249 3 124 3 249 — — — — 500 2 124 2 249 3 124 3 223 3 233 1k 1 249 2 124 2 249 3 111 3 116 2.
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Table 14.6 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 14.7 and 14.8 list the maximum rates for external clock input. Table 14.6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pφ φ (MHz) Maximum Bit Rate (bits/s) n N 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 8 250000 0 0 9.
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Table 14.7 Maximum Bit Rates with External Clock Input (Asynchronous Mode) Pφ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 153600 12 3.0000 187500 14.7456 3.6864 230400 16 4.0000 250000 19.6608 4.9152 307200 20 5.0000 312500 24 6.0000 375000 24.576 6.1440 384000 28.7 7.
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14.3 Operation 14.3.1 Overview For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. Asynchronous/synchronous mode and the transmission format are selected in the serial mode register (SCSMR), as shown in table 14.9.
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Table 14.
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14.3.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. The transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving.
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Transmit/Receive Formats: Table 14.11 lists the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SCSMR). Table 14.
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When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 14.6 so that the rising edge of the clock occurs at the center of each transmit data bit. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 14.
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Initialization Clear TE and RE bits in SCSCR to 0 Set CKE1 and CKE0 bits in SCSCR (TE and RE bits are 0) (1) Select communication format in SCSMR (2) Set value in SCBRR (3) Wait Has a 1-bit interval elapsed? No Yes Set TE and RE bits in SCSCR to 1 and set RIE, TIE, TEIE, and MPIE bits (4) End Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 14.7 Sample Flowchart for SCI Initialization Transmitting Serial Data (Asynchronous Mode): Figure 14.
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Start of transmission Read TDRE bit in SCSSR (1) No TDRE = 1? Yes Write transmit data to SCTDR and clear TDRE bit in SCSSR to 0 (2) No All data transmitted? Yes Read TEND bit in SCSSR No TEND = 1? Yes No Break output? Yes (3) Set SCPDR and SCPCR Clear TE bit in SCSCR to 0 End of transmission Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 14.8 Sample Flowchart for Transmitting Serial Data Rev. 5.
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In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SCSSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (SCTDR) contains new data, and loads this data from SCTDR into the transmit shift register (SCTSR). 2. After loading the data from SCTDR into SCTSR, the SCI sets the TDRE bit to 1 and starts transmitting.
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Figure 14.9 shows an example of SCI transmit operation in asynchronous mode. 1 Serial data Start bit 0 Parity Stop Start bit bit bit Data D0 D1 D7 0/1 1 0 Parity Stop bit bit Data D0 D1 D7 0/1 1 1 Idle (mark) state TDRE TEND TXI interrupt request generated TXI interrupt handler writes data to SCTDR and clears TDRE bit to 0 TXI interrupt request generated TEI interrupt request generated 1 frame Figure 14.
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Start of reception Read ORER, PER, and FER bits in SCSSR PER ∨ FER ∨ ORER = 1? Yes No Read RDRF bit in SCSSR No (1) (2) Error handling RDRF = 1? Yes Read receive data from SCRDR (3) and clear RDRF bit in SCSSR to 0 No All data received? Yes Clear RE bit in SCSCR to 0 End of reception Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 14.10 Sample Flowchart for Receiving Serial Data Rev. 5.
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Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? Yes No Framing error handling No Clear RE bit in SCSCR to 0 PER = 1? Yes Parity error handling Clear ORER, PER, and FER bits in SCSSR to 0 End Figure 14.10 Sample Flowchart for Receiving Serial Data (cont) Rev. 5.
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In receiving, the SCI operates as follows: 1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: a. Parity check: The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in SCSMR. b.
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Figure 14.11 shows an example of SCI receive operation in asynchronous mode. 1 Serial data Start bit 0 Parity Stop Start bit bit bit Data D0 D1 D7 0/1 1 0 Parity Stop bit bit Data D0 D1 D7 0/1 1 1 Idle (mark) state RDRF RXI interrupt request generated FER 1 frame RXI interrupt handler reads data and clears RDRF bit to 0 ERI interrupt request generated by framing error Figure 14.11 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit) 14.3.
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Transmitting station Serial communication line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) ID transmit cycle: specifies receiving station (MPB = 0) Data transmit cycle: data transmission to receiving station specified by ID MPB: Multiprocessor bit Figure 14.
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Start of transmission Read TDRE bit in SCSSR TDRE = 1? (1) No Yes Write transmit data to SCTDR and set MPBT bit in SCSSR Clear TDRE bit to 0 Transmission ended? No (2) Yes Read TEND bit in SCSSR TEND = 1? No Yes Break output? No Yes (3) Set SCPDR and SCPCR Clear TE bit SCSCR to 0 End of transmission Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 14.13 Sample Flowchart for Transmitting Multiprocessor Serial Data Rev. 5.
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In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SCSSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (SCTDR) contains new data, and transfers this data from SCTDR into the transmit shift register (SCTSR). 2. After loading the data from SCTDR into SCTSR, the SCI sets the TDRE bit to 1 and starts transmitting.
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Receiving Multiprocessor Serial Data: Figure 14.15 shows a sample flowchart for receiving multiprocessor serial data. The procedure for receiving multiprocessor serial data is: 1. ID receive cycle: Set the MPIE bit in the serial control register (SCSCR) to 1. 2. SCI status check and compare to ID reception: Read the serial status register (SCSSR), check that RDRF is set to 1, then read data from the receive data register (SCRDR) and compare with the processor’s own ID.
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Start of reception Set MPIE bit in SCSCR to 1 (1) Read ORER and FER bits in SCSSR FER = 1 or ORER = 1? No Read RDRF bit in SCSSR No Yes (2) RDRF = 1? Yes Read receive data from SCRDR No Is ID the station's ID? Yes Read ORER and FER bits in SSCSR FER = 1 or ORER = 1? Yes No Read RDRF bit in SCSSR RDRF = 1? (4) No Yes Read receive data from SCRDR No All data received? Yes Clear RE bit in SCSCR to 0 (3) Error handling End of reception Note: Numbers in parentheses refer to steps in the preceding
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Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? Yes No Framing error handling Clear RE bit in SCSCR to 0 Clear ORER and FER bits in SCSSR to 0 End Figure 14.15 Sample Flowchart for Receiving Multiprocessor Serial Data (cont) Rev. 5.
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Figure 14.16 shows an example of SCI receive operation using a multiprocessor format. 1 Serial data Start bit 0 Data (ID1) D0 D1 Stop Start Data bit (data 1) MPB bit D7 1 1 0 D0 D1 Stop MPB bit D7 0 1 1 Idle (mark) state MPIE RDRF RDR value ID1 RXI interrupt request (multiprocessor interrupt) generated, MPIE = 0 RXI interrupt handler reads RDR data and clears RDRF bit to 0 ID is not station's ID, so MPIE bit is set to 1 again Example: Own ID does not match data Figure 14.
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1 Serial data Start bit 0 Data (ID2) D0 D1 MPB D7 1 Data Stop Start bit bit (Data 2) 1 0 D0 D1 Stop MPB bit D7 0 1 1 Idle (mark) state MPIE RDRF RDR value ID1 RXI interrupt request (multiprocessor interrupt) generated, MPIE = 0 ID2 RXI interrupt handler reads RDR data and clears RDRF bit to 0 Data2 ID is that of station, MPIE bit so reception continues set to 1 unchanged and data again is received by RXI interrupt handler Example: Own ID matches data Figure 14.
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14.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 14.
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Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR). See table 14.10. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character.
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Initialization Clear TE and RE bits in SCSCR to 0 Set RIE, TIE, TEIE, MPIE, CKE1, and CKE0 bits in SCSCR (TE and RE are 0) (1) Set transmit/receive format in SCSMR (2) Set value in SCBRR (3) Wait Has a 1-bit period elapsed? No Yes Set TE and RE bits in SCSCR to 1 and set RIE, TIE, TEIE, and MPIE bits (4) End Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 14.18 Sample Flowchart for SCI Initialization Transmitting Serial Data (Synchronous Mode): Figure 14.
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Start of transmission Read TDRE bit in SCSSR TDRE = 1? (1) No Yes Write transmit data to SCTDR and clear TDRE bit in SCSSR to 0 All data transmitted? No (2) Yes Read TEND bit in SCSSR TEND = 1? No Yes Clear TE bit in SCSCR to 0 End of transmission Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 14.19 Sample Flowchart for Transmitting Serial Data Rev. 5.
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In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SCSSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (SCTDR) contains new data and loads this data from SCTDR into the transmit shift register (SCTSR). 2. After loading the data from SCTDR into SCTSR, the SCI sets the TDRE bit to 1 and starts transmitting.
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Receiving Serial Data (Synchronous Mode): Figure 14.21 shows a sample flowchart for receiving serial data. When switching from asynchronous mode to synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled. The procedure for receiving serial data is: 1. Receive error handling: If a receive error occurs, read the ORER bit in SCSSR to identify the error.
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Start of reception Read ORER bit in SCSSR ORER = 1? Yes No (1) Read RDRF bit in SCSSR No (2) Error handling RDRF = 1? Yes Read receive data from SCRDR (3) and clear RDRF bit in SCSSR to 0 No All data received? Yes Clear RE bit in SCSCR to 0 End of reception Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 14.21 Sample Flowchart for Receiving Serial Data Rev. 5.
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Error handling No ORER = 1? Yes Overrun error handling Clear ORER bit in SCSSR to 0 End Figure 14.21 Sample Flowchart for Receiving Serial Data (cont) In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from SCRSR into SCRDR.
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Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request generated RXI interrupt handler reads data and clears RDRF bit to 0 RXI interrupt request generated ERI interrupt request generated by overrun error 1 frame Figure 14.22 Example of SCI Receive Operation Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 14.23 shows a sample flowchart for transmitting and receiving serial data simultaneously.
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Start of transmission/reception Read TDRE bit in SCSSR No (1) TDRE = 1? Yes Write transmit data to SCTDR and clear TDRE bit in SCSSR to 0 Read ORER bit in SCSSR ORER = 1? Yes (2) No Read RDRF bit in SCSSR No Error processing (3) RDRF = 1? Yes Read receive data from SCRDR and clear RDRF bit in SCSSR to 0 No (4) All data transmitted/received? Yes Clear TE and RE bits in SCSCR to 0 End of transmission/reception Notes: 1.
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14.4 SCI Interrupts The SCI has four interrupt sources transmit-end (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI). Table 14.13 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCSCR). Each interrupt request is sent separately to the interrupt controller. TXI is requested when the TDRE bit in SCSSR is set to 1.
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14.5 Usage Notes Note the following points when using the SCI. SCTDR Writing and TDRE Flag: The TDRE bit in the serial status register (SCSSR) is a status flag indicating loading of transmit data from SCTDR into SCTSR. The SCI sets TDRE to 1 when it transfers data from SCTDR to SCTSR. Data can be written to SCTDR regardless of the TDRE bit state. If new data is written in SCTDR when TDRE is 0, however, the old data stored in SCTDR will be lost because the data has not yet been transferred to SCTSR.
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TEND Flag and TE Bit Processing: The TEND flag is set to 1 during transmission of the stop bit of the last data. Consequently, if the TE bit is cleared to 0 immediately after setting of the TEND flag has been confirmed, the stop bit will be in the process of transmission and will not be transmitted normally. Therefore, the TE bit should not be cleared to 0 for at least 0.5 serial clock cycles (or 1.5 cycles if two stop bits are used) after setting of the TEND flag is confirmed.
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The receive margin in asynchronous mode can therefore be expressed as in equation 1. Equation 1: M = 0.5 − Where: 1 D − 0.5 (1 + F) × 100% − (L − 0.5)F − 2N N M = Receive margin (%) N = Ratio of clock frequency to bit rate (N = 16) D = Clock duty cycle (D = 0 to 1.0) L = Frame length (L = 9 to 12) F = Absolute deviation of clock frequency From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as in equation 2. Equation 2: M = (0.5 – 1/(2 × 16)) × 100% = 46.
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Rev. 5.
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Section 15 Smart Card Interface 15.1 Overview As an added serial communications interface function, the SCI supports an IC card (smart card) interface that conforms to the data transfer protocol (asynchronous half-duplex character transmission protocol) of the ISO/IEC7816-3 (Identification Card) standard. Register settings are used to switch between the normal serial communication interface and the smart card interface. 15.1.
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15.1.2 Block Diagram Bus interface Figure 15.1 shows a block diagram of the smart card interface.
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15.1.3 Pin Configuration Table 15.1 summarizes the smart card interface pins. Table 15.1 Smart Card Interface Pins Pin Name Abbreviation I/O Function Serial clock pin SCK0 Output Clock output Receive data pin RxD0 Input Receive data input Transmit data pin TxD0 Output Transmit data output 15.1.4 Smart Card Interface Registers Table 15.2 summarizes the registers used by the smart card interface.
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15.2 Register Descriptions This section describes the registers added for the smart card interface and the bits whose functions are changed. 15.2.1 Smart Card Mode Register (SCSCMR) The smart card mode register (SCSCMR) is an 8-bit readable/writable register that selects smart card interface functions. SCSCMR bits 0, 2, and 3 are initialized to H'00 by a reset and in standby mode.
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Bit 0—Smart Card Interface Mode Select (SMIF): Enables the smart card interface function. Bit 0 : SMIF Description 0 Smart card interface function disabled 1 Smart card interface function enabled 15.2.2 (Initial value) Serial Status Register (SCSSR) In smart card interface mode, the function of SCSSR bit 4 is changed. The setting conditions for bit 2, the TEND bit, are also changed.
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Bits 3 to 0: These bits have the same function as in the ordinary SCI. See section 14, Serial Communication Interface (SCI), for more information. The setting conditions for bit 2, the transmit end bit (TEND), are changed as follows.
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15.3.2 Pin Connections Figure 15.2 shows the pin connection diagram for the smart card interface. During communication with an IC card, transmission and reception are both carried out over the same data transfer line, so connect the TxD and RxD pins on the chip. Pull up the data transfer line to the power supply VCC side with a register. When using the clock generated by the smart card interface on an IC card, input the SCK pin output to the IC card’s CLK pin.
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15.3.3 Data Format Figure 15.3 shows the data format for the smart card interface. In this mode, parity is checked every frame while receiving and error signals sent to the transmitting side whenever an error is detected so that data can be re-transmitted. During transmission, error signals are sampled and data re-transmitted whenever an error signal is detected.
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5. The transmitting side transmits the next frame of data unless it receives an error signal. If it does receive an error signal, it returns to step 2 to re-transmit the erroneous data. 15.3.4 Register Settings Table 15.3 shows the bit map of the registers that the smart card interface uses. Bits shown as 1 or 0 must be set to the indicated value. The settings for the other bits are described below. Table 15.
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In the inverse convention type, the logical 1 level is state A, the logical 0 level is state Z, and communication is MSB first. The start character data is H'3F. Parity is even (from the smart card standard), and so the parity bit is 0, which corresponds to state Z. Only data bits D7–D0 are inverted by the SINV bit. To invert the parity bit, set the O/E bit in SCSMR to odd parity mode. This applies to both transmission and reception.
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Table 15.4 Relationship of n to CKS1 and CKS0 n CKS1 CKS0 0 0 0 1 0 1 2 1 0 3 1 1 Table 15.5 Examples of Bit Rate B (Bits/s) for SCBRR Settings (n = 0) Pφ (MHz) N 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 0 9600.0 13440.9 14400.0 17473.1 19200.0 21505.4 24193.5 1 4800.0 6720.4 7200.0 8736.6 9600.0 10752.7 12096.8 2 3200.0 4480.3 4800.0 5824.4 6400.0 7168.5 8064.5 Note: The bit rate is rounded to one decimal place.
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Table 15.7 Maximum Bit Rates for Frequencies (Smart Card Interface Mode) Pφ (MHz) Maximum Bit Rate (Bits/s) N n 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 The bit rate error is found as follows: Error (%) = ( 1488 × Pφ × 106 − 1) × 100 × B × (N + 1) 22n−1 Table 15.8 shows the relationship between transmit/receive clock register set values and output states on the smart card interface. Table 15.
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15.3.6 Data Transmission and Reception Initialization: Initialize the SCI using the following procedure before sending or receiving data. Initialization is also required for switching from transmit mode to receive mode or from receive mode to transmit mode. Figure 15.5 shows a flowchart of the initialization process. 1. Clear TE and RE in the serial control register (SCSCR) to 0. 2. Clear error flags FER/ERS, PER, and ORER to 0 in the serial status register (SCSSR). 3.
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Initialization Clear TE and RE bits in SCSCR to 0 (1) Clear FER/ERS, PER and ORER flags in SCSSR to 0 (2) Set parity in O/E bit, set clock in CKS1 and CKS0 bits, and set C/A, in SCSMR (3) Set SMIF, SDIR, and SINV bits in SCSMR (4) Set value in SCBRR (5) Set clock in CKE1 and CKE0 bits, and clear TIE, RIE, TE, RE, MPIE, and TEIE bits to 0, in SCSCR (6) Wait Has a 1-bit interval elapsed? No Yes Set TIE, RIE, TE, and RE bits in SCSCR (7) End Note: Numbers in parentheses refer to steps in the pr
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Serial Data Transmission: The processing procedures in the smart card mode differ from ordinary SCI processing because data is retransmitted when an error signal is sampled during a data transmission. This results in the transmission processing flowchart shown in figure 15.6. 1. Initialize the smart card interface mode as described in Initialization above. 2. Check that the FER/ERS bit in SCSSR is cleared to 0. 3. Repeat steps 2 and 3 until the TEND flag in SCSSR is set to 1. 4.
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Start Initialize (1) Start of transmission FER/ERS = 0? (2) No Yes Error handling No TEND = 1? (3) Yes Write transmit data in SCTDR and clear TDRE flag in SCSSR to 0 (4) All data transmitted? (5) No Yes FER/ERS = 0? No Yes Error handling No TEND = 1? Yes Clear TE bit in SCSCR to 0 (6) End of transmission Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 15.6 Transmission Flowchart Rev. 5.
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Serial Data Reception: The processing procedures in smart card mode are the same as in ordinary SCI processing. The reception processing flowchart is shown in figure 15.7. 1. Initialize the smart card interface mode as described above in Initialization and in figure 15.5. 2. Check that the ORER and PER flags in SCSSR are cleared to 0. If either flag is set, clear both to 0 after performing the appropriate error handling procedures. 3. Repeat steps 2 and 3 until the RDRF flag is set to 1. 4.
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Start Initialize (1) Start of reception ORER = 0 or PER = 0? (2) No Yes Error handling No RDRF = 1? (3) Yes Write receive data from SCRDR and clear RDRF flag in SCSSR to 0 (4) All data received? (5) No Yes Clear RE bit in SCSCR to 0 (6) End of reception Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 15.7 Reception Flowchart (Example) Rev. 5.
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Switching Modes: When switching from receive mode to transmit mode, check that the receive operation is completed before starting initialization, clearing RE to 0, and setting TE to 1. The RDRF, PER, and ORER flags can be used to check if reception is completed. When switching from transmit mode to receive mode, check that the transmit operation is completed before starting initialization, clearing TE to 0, and setting RE to 1. The TEND flag can be used to check if transmission is completed.
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372 clock cycles 186 clock cycles 0 185 371 0 185 371 0 Base clock Start bit Receive data (RxD) D0 Synchronization sampling timing Data sampling timing Figure 15.8 Receive Data Sampling Timing in Smart Card Mode The receive margin is found from the following equation: For smart card mode: M = (0.5 − Where: 1 D − 0.5 (1 + F) × 100% ) − (L − 0.5)F − 2N N M = Receive margin (%) N = Ratio of bit rate to clock (N = 372) D = Clock duty (D = 0 to 1.
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15.4.2 Retransmission (Receive and Transmit Modes) Retransmission when SCI is in Receive Mode: Figure 15.9 shows the retransmission operation in the SCI receive mode. 1. When the received parity bit is checked and an error is found, the PER bit in SCSSR is automatically set to 1. If the RIE bit in SCSCR is enabled at this time, an ERI interrupt is requested. Be sure to clear the PER bit before the next parity bit is sampled. 2. The RDRF bit in SCSSR is not set in the frame that caused the error. 3.
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Retransmission when SCI is in Transmit Mode: Figure 15.10 shows the retransmission operation in the SCI transmit mode. 1. After transmission of one frame is completed, the FER/ERS bit in SCSSR is set to 1 when a error signal is returned from the receiving side. If the RIE bit in SCSCR is enabled at this time, an ERI interrupt is requested. Be sure to clear the FER/ERS bit before the next parity bit is sampled. 2.
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Section 16 Serial Communication Interface with FIFO (SCIF) 16.1 Overview The SH7709S has a two-channel serial communication interface with FIFO (SCIF) that supports asynchronous serial communication. It also has 16-stage FIFO registers for both transmission and reception that enable the SH7709S to perform efficient high-speed continuous communication. 16.1.1 Features • Asynchronous serial communication:  Serial data communication is performed by start-stop in character units.
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16.1.2 Block Diagram Bus interface Figure 16.1 shows a block diagram of the SCIF.
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Figures 16.2 to 16.4 show the SCIF I/O port pins. SCIF pin I/O and data control is performed by bits 11 to 8 of SCPCR and bits 5 and 4 of SCPDR. For details, see section 14.2.8, SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR).
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Reset R D SCP4MD0 Q C Internal data bus PCRW Reset Q R D SCP4MD1 C PCRW Reset SCPT[4]/TxD2 R Q D SCP4DT1 C SCIF PDRW Output enable Serial transmission output Legend PCRW: SCPCR write PDRW: SCPDR write Figure 16.3 SCPT[4]/TxD2 Pin Rev. 5.
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SCIF SCPT[4]/RxD2 Serial receive data PDRR* Internal data bus Legend PDRR: SCPDR read Note: * When reading the RxD2 pin, set the RE bit in SCSCR to 1. Figure 16.4 SCPT[4]/RxD2 Pin 16.1.3 Pin Configuration The SCIF has the serial pins summarized in table 16.1. Table 16.
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16.1.4 Register Configuration Table 16.2 summarizes the SCIF internal registers. These registers specify the data format and bit rate, and control the transmitter and receiver sections. Table 16.
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16.2 Register Descriptions 16.2.1 Receive Shift Register (SCRSR) The receive shift register (SCRSR) receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to SCFRDR, the receive FIFO data register. The CPU cannot read or write to SCRSR directly. 16.2.
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16.2.4 Transmit FIFO Data Register (SCFTDR) The transmit FIFO data register (SCFTDR) is a FIFO register comprising sixteen 8-bit stages that stores data for serial transmission. When the SCIF detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCFTDR into SCTSR and starts serial transmission. Continuous serial transmission is performed until there is no transmit data left in SCFTDR. The CPU can always write to SCFTDR.
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Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the parity of receive data. Bit 5: PE Description 0 Parity bit not added or checked Parity bit added and checked* 1 (Initial value) Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting.
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Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): Select the internal clock source of the onchip baud rate generator. According to the setting of the CKS1 and CKS0 bits four clock sources are available. Pφ, Pφ/4, Pφ/16 and Pφ/64. For further information on the clock source, bit rate register settings, and baud rate, see section 16.2.8, Bit Rate Register (SCBRR). Bit 1: CKS1 Bit 0: CKS0 Description 0 0 Pφ 1 Pφ/4 0 Pφ/16 1 Pφ/64 1 (Initial value) Note: Pφ: Peripheral clock 16.2.
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Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full (RXI) and receive-error (ERI) interrupts requested when serial receive data is transferred from the receive shift register (SCRSR) to the receive FIFO data register (SCFRDR), when the quantity of data in the receive FIFO register becomes more than the specified receive trigger number, and when the RDRF flag in SCSSR is set to1.
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Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): Select the SCIF clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output or serial clock input. The CKE0 setting is valid only when the SCIF is operating on the internal clock (CKE1 = 0). The CKE0 setting is ignored when an external clock source is selected (CKE1 = 1).
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Bit 7—Receive Error (ER): Indicates the occurrence of a framing error, or of a parity error when receiving data that includes parity.
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Bit 5—Transmit FIFO Data Empty (TDFE): Indicates that data has been transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the quantity of data in SCFTDR has become less than the transmission trigger number specified by the TTRG1 and TTRG0 bits in the FIFO control register (SCFCR), and writing of transmit data to SCFTDR is enabled.
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Bit 3—Framing Error (FER): Indicates a framing error in the data read from the receive FIFO data register (SCFRDR).
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Bit 1—Receive FIFO Data Full (RDF): Indicates that receive data has been transferred to the receive FIFO data register (SCFRDR), and the quantity of data in SCFRDR has become greater than the receive trigger number specified by the RTRG1 and RTRG0 bits in the FIFO control register (SCFCR).
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Upper 8 bits: 15 14 13 12 11 10 9 8 PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bits 15 to 12—Number of Parity Errors 3 to 0 (PER3 to PER0): Indicate the quantity of data including a parity error in the receive data stored in the receive FIFO data register (SCFRDR). The value indicated by bits 15 to 12 represents the number of parity errors in SCFRDR.
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Table 16.3 SCSMR Settings SCSMR Settings n Clock Source CKS1 CKS0 0 Pφ 0 0 1 Pφ/4 0 1 2 Pφ/16 1 0 3 Pφ/64 1 1 Note: The bit rate error is given by the following formula: Error (%) = Pφ (N+1) × 64 × 22n−1 × B × 106 − 1 × 100 Table 16.4 lists examples of SCBRR settings. Table 16.4 Bit Rates and SCBRR Settings Pφ φ (MHz) 2 2.097152 2.4576 Bit Rate (bits/s) n N Error (% %) n N Error (% %) n N Error (% %) 110 1 141 0.03 1 148 –0.04 1 174 –0.26 150 1 103 0.
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Pφ φ (MHz) 3 3.6864 4 Bit Rate (bits/s) n N Error (% %) n N Error (% %) n N Error (% %) 110 1 212 0.03 2 64 0.70 2 70 0.03 150 1 155 0.16 1 191 0.00 1 207 0.16 300 1 77 0.16 1 95 0.00 1 103 0.16 600 0 155 0.16 0 191 0.00 0 207 0.16 1200 0 77 0.16 0 95 0.00 0 103 0.16 2400 0 38 0.16 0 47 0.00 0 51 0.16 4800 0 19 –2.34 0 23 0.00 0 25 0.16 9600 0 9 –2.34 0 11 0.00 0 12 0.16 19200 0 4 –2.34 0 5 0.00 0 6 –6.
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Pφ φ (MHz) 6.144 7.3728 8 Bit Rate (bits/s) n N Error (% %) n N Error (% %) n N Error (% %) 110 2 108 0.08 2 130 –0.07 2 141 0.03 150 2 79 0.00 2 95 0.00 2 103 0.16 300 1 159 0.00 1 191 0.00 1 207 0.16 600 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 0.00 0 11 0.00 0 12 0.
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Pφ φ (MHz) 14.7456 Error (% %) 16 19.6608 Bit Rate (bits/s) n N 110 3 64 0.70 3 70 0.03 3 86 0.31 3 88 –0.25 150 2 191 0.00 2 207 0.16 2 255 0.00 2 64 0.16 300 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 n N Error (% %) n N Error (% %) 20 n Error (% %) N 600 1 191 0.00 1 207 0.16 1 255 0.00 1 64 0.16 1200 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 2400 0 191 0.00 0 207 0.16 0 255 0.00 0 64 0.16 4800 0 95 0.
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Table 16.5 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Table 16.6 list the maximum rates for external clock input. Table 16.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pφ φ (MHz) Maximum Bit Rate (bits/s) n N 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 8 250000 0 0 9.8304 307200 0 0 12 375000 0 0 14.
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Table 16.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) Pφ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 153600 12 3.0000 187500 14.7456 3.6864 230400 16 4.0000 250000 19.6608 4.9152 307200 20 5.0000 312500 24 6.0000 375000 24.576 6.1440 384000 28.7 7.
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16.2.9 FIFO Control Register (SCFCR) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 RTRG1 RTRG0 TTRG1 TTRG0 MCE TFRST RFRST LOOP 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The FIFO control register (SCFCR) resets the quantity of data in the transmit and receive FIFO registers, sets the trigger data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and written to by the CPU.
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Bit 3—Modem Control Enable (MCE): Enables modem control signals CTS and RTS. Bit 3: MCE Description 0 Modem signal disabled* 1 Modem signal enabled (Initial value) Note: * CTS is fixed at active 0 regardless of the input value, and RTS is also fixed at 0. Bit 2—Transmit FIFO Data Register Reset (TFRST): Disables the transmit data in the transmit FIFO data register and resets the data to the empty state.
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16.2.10 FIFO Data Count Register (SCFDR) SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of receive data in SCFRDR with the lower 8 bits. SCFDR can always be read by the CPU.
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16.3 Operation 16.3.1 Overview For serial communication, the SCIF has an asynchronous mode in which characters are synchronized individually. Refer to section 14.3.2, Operation in Asynchronous Mode. The SCIF has a 16-byte FIFO buffer for both transmit and receive operations, reducing the overhead of the CPU, and enabling continuous high-speed communication. Moreover, it has RTS and CTS signals as modem control signals.
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Table 16.8 SCSCR Settings and SCIF Clock Source Selection SCSCR Settings Mode Asynchronous mode SCIF Transmit/Receive Clock Bit 1 CKE1 Bit 0 CKE0 Clock Source SCK Pin Function 0 0 Internal SCIF does not use the SCK pin 1 1 Outputs a clock with a frequency 16 times the bit rate 0 External Inputs a clock with frequency 16 times the bit rate 1 16.3.2 Serial Operation Transmit/Receive Formats: Table 16.9 lists the eight communication formats that can be selected.
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Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCIF transmit/receive clock. The clock source is selected by bits CKE1 and CKE0 in the serial control register (SCSCR) (table 16.8). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCIF operates on an internal clock, it can output a clock signal at the SCK pin.
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Initialization Clear TE and RE bits in SCSCR to 0 (1) Set TFRST and RFRST bits in SCFCR to 1 Set CKE1 and CKE0 bits in SCSCR (leaving TE and RE bits cleared to 0) Set communication format in SCSMR (2) Set value in SCBRR (3) Wait 1-bit interval elapsed? Yes No (4) Set RTRG1-0, TTRG1-0, and MCE in SCFCR Clear TFRST and RFRST bits to 0 Set TE and RE bits in SCSCR to 1,and set RIE, TIE, TEIE, and MPIE bits End Note: Numbers in parentheses refer to steps in the preceding procedure description.
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• Serial data transmission Figure 16.6 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. 1. SCIF status check and transmit data write: Read serial status register (SCSSR) and check that the TDFE flag is set to 1, then write transmit data to the transmit FIFO data register (SCFTDR), read 1 from the TDFE and TEND flags, then clear these flags to 0.
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Start of transmission Read TDFE bit in SCSSR TDFE= 1? (1) No Yes Write transmit data (16 - transmit trigger set number) to SCFTDR, read 1 from TDFE bit and TEND flag in SCSSR, then clear to 0 All data transmitted? (2) No Yes Read TEND bit in SCSSR TEND= 1? No Yes Break output? No Yes (3) Set SCPDR and SCPCR Clear TE bit in SCSCR to 0 End of transmission Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 16.
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In serial transmission, the SCIF operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that the TDFE flag in the serial status register (SCSSR) is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is (16 – transmit trigger setting). 2.
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Figure 16.7 shows an example of the operation for transmission. 1 Serial data Start bit D0 0 Parity Stop Start bit bit bit Data D1 D7 0/1 1 0 Parity Stop bit bit Data D0 D1 D7 0/1 1 1 Idle (mark) state TDFE TEND TXI interrupt request Data written to SCFTDR and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler TXI interrupt request One frame Figure 16.7 Example of Transmit Operation (8-Bit Data, Parity, One Stop Bit) 4.
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• Serial data reception Figures 16.9 and 16.10 show a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. 1. Receive error handling and break detection: Read the DR, ER, and BRK flags in SCSSR to identify any error, perform the appropriate error handling, then clear the DR, ER, and BRK flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RxD pin. 2.
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Start of reception Read ORER, PER, FER flags in SCSSR PER v FER v ORER = 1? No (1) Yes Error handling Read RDF flag in SCSSR No (2) RDF = 1? Yes Read receive data from SCFRDR, and clear RDF flag in SCSSR to 0 No (3) All data received? Yes Clear RE bit in SCSCR to 0 End of reception Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 16.9 Sample Flowchart for Receiving Serial Data Rev. 5.
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1. Whether a framing error or parity error has occurred in the receive data read from SCFRDR can be ascertained from the FER and PER bits in SCSSR. 2. When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set. However, note that the last data in SCFRDR is H'00 and the break data in which a framing error occurred is stored.
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In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. a. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. b.
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Figure 16.11 shows an example of the operation for reception. 1 Serial data Start bit 0 Parity Stop Start bit bit bit Data D0 D1 D7 0/1 1 0 Parity Stop bit bit Data D0 D1 D7 0/1 1 1 Idle (mark) state RDF RXI interrupt request FER One frame Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler ERI interrupt request generated by receive error Figure 16.11 Example of SCIF Receive Operation (8-Bit Data, Parity, One Stop Bit) 5.
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16.4 SCIF Interrupts The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI), receive-data-full (RXI), and break (BRI). Table 16.10 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE and RIE bits in SCSCR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources.
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16.5 Usage Notes Note the following when using the SCIF. 1. SCFTDR Writing and TDFE Flag: The TDFE flag in the serial status register (SCSSR) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR) has fallen below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR). After TDFE is set, transmit data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous transmission.
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5. TEND Flag and TE Bit Processing: The TEND flag is set to 1 during transmission of the stop bit of the last data. Consequently, if the TE bit is cleared to 0 immediately after setting of the TEND flag has been confirmed, the stop bit will be in the process of transmission and will not be transmitted normally. Therefore, the TE bit should not be cleared to 0 for at least 0.5 serial clock cycles (or 1.5 cycles if two stop bits are used) after setting of the TEND flag is confirmed. 6.
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Equation 2: When D = 0.5 and F = 0: M = (0.5 – 1/(2 × 16)) × 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Rev. 5.
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Rev. 5.
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Section 17 IrDA 17.1 Overview The SH7709S has an on-chip Infrared Data Association (IrDA) interface which is based on the IrDA 1.0 system and can perform infrared communication. It also can be used as the SCIF by making register settings. 17.1.1 Features • Conforms to the IrDA 1.
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17.1.2 Block Diagram Figure 17.1 shows a block diagram of the IrDA. Clock input SCK TxD Transfer clock TxD1 Modulation unit SCIF RxD Demodulation unit RxD1 IrDA Switching IrDA/SCIF Legend SCIF: Serial communication interface with FIFO Figure 17.1 Block Diagram of IrDA Rev. 5.
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Figures 17.2 to 17.4 show the IrDA I/O port pins. SCIF pin I/O and data control is performed by bits 7 to 4 of SCPCR and bits 3 and 2 of SCPDR. For details, see section 14.2.8, SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR).
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Reset R D SCP2MD0 Q C PCRW Reset Internal data bus R Q D SCP2MD1 C PCRW Reset SCPT[2]/TxD1 R Q D SCP2DT1 C IrDA PDRW Output enable Serial transfer output Legend PCRW: SCPCR write PDRW: SCPDR write Figure 17.3 SCPT[2]/TxD1 Pin Rev. 5.
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IrDA SCPT[2]/RxD1 Serial receive data Internal data bus PDRR* Legend PDRR: SCPDR read Note: * When reading the RxD1 pin, set the RE bit in SCSCR to 1. Figure 17.4 SCPT[2]/RxD1 Pin 17.1.3 Pin Configuration The IrDA has the serial pins summarized in table 17.1. Table 17.
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17.1.4 Register Configuration The IrDA has the internal registers shown in table 17.2. These registers select IrDA or SCIF mode, specify the data format and a bit rate, and control the transmit and receive units. Table 17.
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17.2 Register Description Specifications of the registers in the IrDA are the same as those in the SCIF except for the serial mode register described below. Therefore, refer to section 16, Serial Communication Interface with FIFO (SCIF), for details of these registers. 17.2.
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Bits 6 to 3—Ir Clock Select Bits (ICK3 to ICK0) Bit 2—Output Pulse Width Select (PSEL): PSEL selects an IrDA output pulse width that is 3/16 of the bit length for 115 kbps or 3/16 of the bit length for the selected baud rate. The Ir clock select bits should be set properly to fix the output pulse width at 3/16 of the bit length for 115 kbps by setting the PSEL bit to 1.
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17.3 Operation Description The IrDA module can perform infrared communication conforming to IrDA 1.0 by connecting infrared transmit/receive units. The serial communication interface unit includes a 16-stage FIFO buffer in the transmit unit and the receive unit, allowing CPU overhead to be reduced and continuous high-speed communication to be performed. This module also supports DMAC data transfer.
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17.3.3 Receiving Received 3/16 IR frame bit-width pulses are demodulated and converted to a UART frame, as shown in figure 17.5. Demodulation to 0 is performed for pulse output, and demodulation to 1 is performed for no pulse output. UART frame Data Start bit 0 1 0 1 0 Stop bit 0 1 Transmit 1 0 1 Receive IR frame Data Start bit 0 1 0 Bit cycle 1 0 Stop bit 0 1 1 3/16-bit cycle pulse width Figure 17.5 Transmit/Receive Operation Rev. 5.
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Section 18 Pin Function Controller 18.1 Overview The pin function controller (PFC) is composed of registers for selecting the function of multiplexed pins and the input/output direction. The pin function and input/output direction can be selected for each pin individually without regard to the operating mode of the chip. Table 18.1 lists the multiplexed pins. Table 18.
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Port Port Function (Related Module) Other Function (Related Module) C PTC0 input/output (port)/PINT0 input (INTC) MCS0 output (BSC) D PTD7 input/output (port) DACK1 output (DMAC) D PTD6 input (port) DREQ1 input (DMAC) D PTD5 input/output (port) DACK0 output (DMAC) D PTD4 input (port) DREQ0 input (DMAC) D PTD3 input/output (port) WAKEUP output (WTC) D PTD2 input/output (port) RESETOUT output D PTD1 input/output (port) DRAK0 output (DMAC) D PTD0 input/output (port) DRAK1 output (D
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Port Port Function (Related Module) Other Function (Related Module) G PTG1 input (port) AUDATA1 output (AUD) G PTG0 input (port) AUDATA0 output (AUD) H PTH7 input/output (port) TCLK input/output (TMU) H PTH6 input (port) AUDCK input (AUD) H PTH5 input (port) ADTRG input (ADC) H PTH4 input (port)/IRQ4 input (INTC) IRQ4 input (INTC) H PTH3 input (port)/IRQ3 input (INTC) IRQ3 input (INTC) H PTH2 input (port)/IRQ2 input (INTC) IRQ2 input (INTC) H PTH1 input (port)/IRQ1 input (INTC)
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Port Port Function (Related Module) Other Function (Related Module) L PTL4 input (port) AN4 input (ADC) L PTL3 input (port) AN3 input (ADC) L PTL2 input (port) AN2 input (ADC) L PTL1 input (port) AN1 input (ADC) L PTL0 input (port) AN0 input (ADC) SCPT SCPT7 input (port)/IRQ5 input (INTC) CTS2 input (UART ch 3)/IRQ5 input (INTC) SCPT SCPT6 input/output (port) RTS2 output (UART ch 3) SCPT SCPT5 input/output (port) SCK2 input/output (UART ch 3) SCPT SCPT4 input (port) RxD2 input (
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18.2 Register Configuration Table 18.2 summarizes the registers of the pin function controller. Table 18.
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18.3 Register Descriptions 18.3.1 Port A Control Register (PACR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA7 PA7 PA6 PA6 PA5 PA5 PA4 PA4 PA3 PA3 PA2 PA2 PA1 PA1 PA0 PA0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port A control register (PACR) is a 16-bit readable/writable register that selects the pin functions.
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18.3.2 Port B Control Register (PBCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PB7 PB7 PB6 PB6 PB5 PB5 PB4 PB4 PB3 PB3 PB2 PB2 PB1 PB1 PB0 PB0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port B control register (PBCR) is a 16-bit readable/writable register that selects the pin functions.
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18.3.3 Port C Control Register (PCCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PC7 PC7 PC6 PC6 PC5 PC5 PC4 PC4 PC3 PC3 PC2 PC2 PC1 PC1 PC0 PC0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port C control register (PCCR) is a 16-bit readable/writable register that selects the pin functions.
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18.3.4 Port D Control Register (PDCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD7 PD7 PD6 PD6 PD5 PD5 PD4 PD4 PD3 PD3 PD2 PD2 PD1 PD1 PD0 PD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port D control register (PDCR) is a 16-bit readable/writable register that selects the pin functions.
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18.3.5 Port E Control Register (PECR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PE7 PE7 PE6 PE6 PE5 PE5 PE4 PE4 PE3 PE3 PE2 PE2 PE1 PE1 PE0 PE0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1/0 0 1 0 1 0 1 0 1 0 1 0 1 0 1/0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port E control register (PECR) is a 16-bit readable/writable register that selects the pin functions.
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18.3.6 Port F Control Register (PFCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PF7 PF7 PF6 PF6 PF5 PF5 PF4 PF4 PF3 PF3 PF2 PF2 PF1 PF1 PF0 PF0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1/0 0 1/0 0 1/0 0 1/0 0 1 0 1 0 1 0 1 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port F control register (PFCR) is a 16-bit readable/writable register that selects the pin functions.
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18.3.7 Port G Control Register (PGCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PG7 PG7 PG6 PG6 PG5 PG5 PG4 PG4 PG3 PG3 PG2 PG2 PG1 PG1 PG0 PG0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1 0 1 0 1/0 0 1 0 1/0 0 1/0 0 1/0 0 1/0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port G control register (PGCR) is a 16-bit readable/writable register that selects the pin functions.
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Bit (2n + 1) Bit 2n PGnMD1 PGnMD0 Pin Function 0 0 Other function (n = 1–3, 5) (see table 18.1) (Initial value) (ASEMD0 = 0) 0 1 Reserved 1 0 Port input (Pull-up MOS: on) 1 1 Port input (Pull-up MOS: off) (Initial value) (ASEMD0 = 1) (n = 1 to 3, 5) Bit (2n + 1) Bit 2n PGnMD1 PGnMD0 0 0 Other function (n = 4, 6, 7) (see table 18.
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Bits 15 and 14—PH7 Mode 1, 0 (PH7MD1, PH7MD0): These bits select the pin functions and perform input pull-up MOS control. Bit 15 Bit 14 PH7MD1 PH7MD0 Pin Function 0 0 Other function (see table 18.
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18.3.9 Port J Control Register (PJCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PJ7 PJ7 PJ6 PJ6 PJ5 PJ5 PJ4 PJ4 PJ3 PJ3 PJ2 PJ2 PJ1 PJ1 PJ0 PJ0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port J control register (PJCR) is a 16-bit readable/writable register that selects the pin functions.
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18.3.10 Port K Control Register (PKCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PK7 PK7 PK6 PK6 PK5 PK5 PK4 PK4 PK3 PK3 PK2 PK2 PK1 PK1 PK0 PK0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port K control register (PKCR) is a 16-bit readable/writable register that selects the pin functions.
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18.3.11 Port L Control Register (PLCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PL7 PL7 PL6 PL6 PL5 PL5 PL4 PL4 PL3 PL3 PL2 PL2 PL1 PL1 PL0 PL0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port L control register (PLCR) is a 16-bit readable/writable register that selects the pin functions.
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18.3.12 SC Port Control Register (SCPCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCP7 SCP7 SCP6 SCP6 SCP5 SCP5 SCP4 SCP4 SCP3 SCP3 SCP2 SCP2 SCP1 SCP1 SCP0 SCP0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The SC port control register (SCPCR) is a 16-bit readable/writable register that selects the pin functions.
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Bits 11 and 10—SCP5 Mode 1 and 0 (SCP5MD1, SCP5MD0): These bits select the pin functions and perform input pull-up MOS control. Bit 11 Bit 10 SCP5MD1 SCP5MD0 Pin Function 0 0 Other function (see table 18.1) 0 1 Port output 1 0 Port input (Pull-up MOS: on) 1 1 Port input (Pull-up MOS: off) (Initial value) Bits 9 and 8—SCP4 Mode 1 and 0 (SCP4MD1, SCP4MD0): These bits select the pin function and perform input pull-up MOS control.
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Bits 5 and 4—SCP2 Mode 1 and 0 (SCP2MD1, SCP2MD0): These bits select the pin function and perform input pull-up MOS control.
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Bits 1 and 0—SCP0 Mode 1 and 0 (SCP0MD1, SCP0MD0): These bits select the pin function and perform input pull-up MOS control.
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Rev. 5.
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Section 19 I/O Ports 19.1 Overview The SH7709S has twelve 8-bit ports (ports A to L and SC). All port pins are multiplexed with other pin functions (the pin function controller (PFC) handles the selection of pin functions and pull-up MOS control). Each port has a data register which stores data for the pins. 19.2 Port A Port A is an 8-bit input/output port with the pin configuration shown in figure 19.1.
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19.2.2 Port A Data Register (PADR) Bit: 7 6 5 4 3 2 1 0 PA7DT PA6DT PA5DT PA4DT PA3DT PA2DT PA1DT PA0DT 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: The port A data register (PADR) is an 8-bit readable/writable register that stores data for pins PTA7 to PTA0. Bits PA7DT to PA0DT correspond to pins PTA7 to PTA0. When the pin function is general output port, if the port is read the value of the corresponding PADR bit is returned directly.
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19.3 Port B Port B is an 8-bit input/output port with the pin configuration shown in figure 19.2. Each pin has an input pull-up MOS, which is controlled by the port B control register (PBCR) in the PFC.
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19.3.2 Port B Data Register (PBDR) Bit: 7 6 5 4 3 2 1 0 PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: The port B data register (PBDR) is an 8-bit readable/writable register that stores data for pins PTB7 to PTB0. Bits PB7DT to PB0DT correspond to pins PTB7 to PTB0. When the pin function is general output port, if the port is read the value of the corresponding PBDR bit is returned directly.
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19.4 Port C Port C is an 8-bit input/output port with the pin configuration shown in figure 19.3. Each pin has an input pull-up MOS, which is controlled by the port C control register (PCCR) in the PFC.
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19.4.2 Port C Data Register (PCDR) Bit: 7 6 5 4 3 2 1 0 PC7DT PC6DT PC5DT PC4DT PC3DT PC2DT PC1DT PC0DT 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: The port C data register (PCDR) is an 8-bit readable/writable register that stores data for pins PTC7 to PTC0. Bits PC7DT to PC0DT correspond to pins PTC7 to PTC0. When the pin function is general output port, if the port is read, the value of the corresponding PCDR bit is returned directly.
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19.5 Port D Port D comprises a 6-bit input/output port and 2-bit input port with the pin configuration shown in figure 19.4. Each pin has an input pull-up MOS, which is controlled by the port D control register (PDCR) in the PFC.
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19.5.2 Port D Data Register (PDDR) Bit: 7 6 5 4 3 2 1 0 PD7DT PD6DT PD5DT PD4DT PD3DT PD2DT PD1DT PD0DT 0 * 0 * 0 0 0 0 R/W R R/W R R/W R/W R/W R/W Initial value: R/W: Note: * Undefined The port D data register (PDDR) is a 6-bit readable/writable and 2-bit read-only register that stores data for pins PTD7 to PTD0. Bits PD7DT to PD0DT correspond to pins PTD7 to PTD0.
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19.6 Port E Port E is an 8-bit input/output port with the pin configuration shown in figure 19.5. Each pin has an input pull-up MOS, which is controlled by the port E control register (PECR) in the PFC. PTE7 (input/output) / AUDSYNC (output) PTE6 (input/output) PTE5 (input/output) / CE2B (output) Port E PTE4 (input/output) / CE2A (output) PTE3 (input/output) PTE2 (input/output) / RAS3U (output) PTE1 (input/output) PTE0 (input/output) / TDO (output) Figure 19.5 Port E 19.6.
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19.6.2 Port E Data Register (PEDR) Bit: 7 6 5 4 3 2 1 0 PE7DT PE6DT PE5DT PE4DT PE3DT PE2DT PE1DT PE0DT 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: The port E data register (PEDR) is an 8-bit readable/writable register that stores data for pins PTE7 to PTE0. Bits PE7DT to PE0DT correspond to pins PTE7 to PTE0. When the pin function is general output port, if the port is read the value of the corresponding PEDR bit is returned directly.
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19.7 Port F Port F is an 8-bit input port with the pin configuration shown in figure 19.6. Each pin has an input pull-up MOS, which is controlled by the port F control register (PFCR) in the PFC.
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19.7.2 Port F Data Register (PFDR) Bit: 7 6 5 4 3 2 1 0 PF7DT PF6DT PF5DT PF4DT PF3DT PF2DT PF1DT PF0DT Initial value: * * * * * * * * R/W: R R R R R R R R Note: * Undefined The port F data register (PFDR) is an 8-bit read-only register that stores data for pins PTF7 to PTF0. Bits PF7DT to PF0DT correspond to pins PTF7 to PTF0. When the function is general input port, if the port is read the corresponding pin level is read. Table 19.12 shows the function of PFDR.
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19.8 Port G Port G comprises a 5-bit input/output port and 3-bit input port with the pin configuration shown in figure 19.7. Each pin has an input pull-up MOS, which is controlled by the port G control register (PGCR) in the PFC.
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19.8.2 Port G Data Register (PGDR) Bit: 7 6 5 4 3 2 1 0 PG7DT PG6DT PG5DT PG4DT PG3DT PG2DT PG1DT PG0DT Initial value: * * * * * * * * R/W: R R R R R R R R Note: * Undefined The port G data register (PGDR) is an 8-bit read-only register that stores data for pins PTG7 to PTG0. Bits PG7DT to PG0DT correspond to pins PTG7 to PTG0. When the function is general input port, if the port is read the corresponding pin level is read. Table 19.14 shows the function of PGDR.
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19.9 Port H Port H comprises a 1-bit input/output port and 7-bit input port with the pin configuration shown in figure 19.8. Each pin has an input pull-up MOS, which is controlled by the port H control register (PHCR) in the PFC. PTH7 (input/output) / TCLK (output) PTH6 (input) / AUDCK (input) PTH5 (input) / ADTRG (input) Port H PTH4 (input) / IRQ4 (input) PTH3 (input) / IRQ3 (input) PTH2 (input) / IRQ2 (input) PTH1 (input) / IRQ1 (input) PTH0 (input) / IRQ0 (input) Figure 19.8 Port H 19.9.
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19.9.2 Port H Data Register (PHDR) Bit: 7 6 5 4 3 2 1 0 PH7DT PH6DT PH5DT PH4DT PH3DT PH2DT PH1DT PH0DT 0 * * * * * * * R/W R R R R R R R Initial value: R/W: Note: * Undefined The port H data register (PHDR) is a 1-bit readable/writable and 7-bit read-only register that stores data for pins PTH7 to PTH0. Bits PH7DT to PH0DT correspond to pins PTH7 to PTH0.
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19.10 Port J Port J is an 8-bit input/output port with the pin configuration shown in figure 19.9. Each pin has an input pull-up MOS, which is controlled by the port J control register (PJCR) in the PFC. PTJ7 (input/output) / STATUS1 (output) PTJ6 (input/output) / STATUS0 (output) PTJ5 (input/output) Port J PTJ4 (input/output) PTJ3 (input/output) / CASU (output) PTJ2 (input/output) / CASL (output) PTJ1 (input/output) PTJ0 (input/output) / RAS3L (output) Figure 19.9 Port J 19.10.
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19.10.2 Port J Data Register (PJDR) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 PJ7DT PJ6DT PJ5DT PJ4DT PJ3DT PJ2DT PJ1DT PJ0DT 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port J data register (PJDR) is an 8-bit readable/writable register that stores data for pins PTJ7 to PTJ0. Bits PJ7DT to PJ0DT correspond to pins PTJ7 to PTJ0. When the pin function is general output port, if the port is read the value of the corresponding PJDR bit is returned directly.
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19.11 Port K Port K is an 8-bit input/output port with the pin configuration shown in figure 19.10. Each pin has an input pull-up MOS, which is controlled by the port K control register (PKCR) in the PFC.
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19.11.2 Port K Data Register (PKDR) Bit: 7 6 5 4 3 2 1 0 PK7DT PK6DT PK5DT PK4DT PK3DT PK2DT PK1DT PK0DT 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: The port K data register (PKDR) is an 8-bit readable/writable register that stores data for pins PTK7 to PTK0. Bits PK7DT to PK0DT correspond to pins PTK7 to PTK0. When the pin function is general output port, if the port is read, the value of the corresponding PKDR bit is returned directly.
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19.12 Port L Port L is an 8-bit input port with the pin configuration shown in figure 19.11. PTL7 (input) / AN7 (input) / DA0 (input) PTL6 (input) / AN6 (input) / DA1 (input) PTL5 (input) / AN5 (input) PTL4 (input) / AN4 (input) Port L PTL3 (input) / AN3 (input) PTL2 (input) / AN2 (input) PTL1 (input) / AN1 (input) PTL0 (input) / AN0 (input) Figure 19.11 Port L 19.12.1 Register Description Table 19.21 summarizes the port L register. Table 19.
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19.12.2 Port L Data Register (PLDR) Bit: 7 6 5 4 3 2 1 0 PL7DT PL6DT PL5DT PL4DT PL3DT PL2DT PL1DT PL0DT Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R The port L data register (PLDR) is an 8-bit read-only register that stores data for pins PTL7 to PTL0. Bits PL7DT to PL0DT correspond to pins PTL7 to PTL0. When the function is general input port, if the port is read, the corresponding pin level is read. Table 19.22 shows the function of PLDR.
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19.13 SC Port The SC port comprises a 4-bit input/output port, 3-bit output port, and 4-bit input port with the pin configuration shown in figure 19.12. Each pin has an input pull-up MOS, which is controlled by the SC port control register (SCPCR) in the PFC.
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19.13.2 SC Port Data Register (SCPDR) Bit: 7 6 5 4 3 2 1 0 SCP7DT SCP6DT SCP5DT SCP4DT SCP3DT SCP2DT SCP1DT SCP0DT Initial value: * 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W Note: * Undefined The SC port data register (SCPDR) is a 7-bit readable/writable and 1-bit read-only register that stores data for pins SCPT7 to SCPT0. Bits SCP7DT to SCP0DT correspond to pins SCPT7 to SCPT0.
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Table 19.24 Read/Write Operation of the SC Port Data Register (SCPDR) SCPnMD1 SCPnMD0 Pin State Read Write 0 0 Other function (see table 18.
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Rev. 5.
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Section 20 A/D Converter 20.1 Overview The SH7709S includes a 10-bit successive-approximation A/D converter allowing selection of up to eight analog input channels. 20.1.1 Features A/D converter features are listed below.
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20.1.2 Block Diagram Bus interface Figure 20.1 shows a block diagram of the A/D converter.
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20.1.3 Input Pins Table 20.1 summarizes the A/D converter’s input pins. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power supply inputs for the analog circuits in the A/D converter. AVcc also functions as the A/D converter reference voltage pin. Table 20.
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20.1.4 Register Configuration Table 20.2 summarizes the A/D converter’s registers. Table 20.
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20.2 Register Descriptions 20.2.
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20.2.2 A/D Control/Status Register (ADCSR) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 ADF ADIE ADST MULTI CKS CH2 CH1 CH0 0 0 0 0 0 0 0 0 R/(W)* R/W R/W R/W R/W R/W R/W R/W Note: * Write 0 to clear the flag. ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter. ADCSR is initialized to H'00 by a reset and in standby mode. Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
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Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin.
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Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the MULTI bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. Channel Selection Description CH2 CH1 CH0 Single Mode (MULTI = 0) Multi Mode and Scan Mode (MULTI = 1) 0 0 0 AN0 (Initial value) AN0 1 AN1 AN0, AN1 0 AN2 AN0 to AN2 1 AN3 AN0 to AN3 0 AN4 AN4 1 AN5 AN4, AN5 1 1 0 1 0 AN6 AN4 to AN6 1 AN7 AN4 to AN7 Rev. 5.
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20.2.3 A/D Control Register (ADCR) Bit: 7 6 5 TRGE1 TRGE0 SCN 0 0 0 0 0 R/W R/W R/W R/W R/W Initial value: R/W: 4 3 RESVD1 RESVD2 2 1 0 — — — 1 1 1 R R R ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion. ADCR is initialized to H'07 by a reset and in standby mode. Bit 7 and 6—Trigger Enable (TRGE1, TRGE0): Enables or disables external triggering of A/D conversion.
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20.3 Bus Master Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the bus master by the upper 8 bits of the 16-bit peripheral data bus. Therefore, although the upper byte can be accessed directly by the bus master, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows. When the upper byte is read, the upper-byte value is transferred directly to the bus master and the lower-byte value is transferred into TEMP.
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20.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has three operating modes: single mode, multi mode, and scan mode. 20.4.1 Single Mode (MULTI = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when conversion ends.
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Note: * Vertical arrows ( ) indicate instruction execution by software. Figure 20.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev. 5.
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20.4.2 Multi Mode (MULTI = 1, SCN = 0) Multi mode should be selected when performing A/D conversions on one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately.
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Note: * Vertical arrows ( ) indicate instruction execution by software. Figure 20.4 Example of A/D Converter Operation (Multi Mode, Channels AN0 to AN2 Selected) Rev. 5.
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20.4.3 Scan Mode (MULTI = 1, SCN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit in the A/D control/status register (ADCSR) is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1)). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately.
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Figure 20.5 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) Rev. 5.00, 09/03, page 628 of 760 Waiting Waiting Waiting Channel 1 (AN1) operating Channel 2 (AN2) operating Channel 3 (AN3) operating Notes: 1. Vertical arrows ( ) indicate instruction execution by software. 2. Data during conversion is ignored.
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20.4.4 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 20.6 shows the A/D conversion timing. Table 20.4 indicates the A/D conversion time. As indicated in figure 20.6, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR.
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Table 20.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Symbol Min Typ Max Min Typ Max A/D conversion start delay tD 17 — 28 10 — 17 Input sampling time tSPL — 129 — — 65 — A/D conversion time tCONV 514 — 525 259 — 266 Note: Values in the table are numbers of states (tcyc). 20.4.5 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGE1 and TRGE0 bits are set to 1 in ADCR, external trigger input is enabled at the ADTRG pin.
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20.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 20.6 Definitions of A/D Conversion Accuracy The A/D converter compares an analog value input from an analog input channel with its analog reference value and converts it to 10-bit digital data. The absolute accuracy of this A/D conversion is the deviation between the input analog value and the output digital value.
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Digital output 111 (2) Full-scale error Digital output Ideal A/D conversion characteristic Ideal A/D conversion characteristic 110 101 100 (4) Nonlinearity error 011 010 001 000 (3) Quantization error 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input voltage FS: Full-scale voltage Actual A/D convertion characteristic (1) Offset error FS Analog input voltage Figure 20.8 Definitions of A/D Conversion Accuracy 20.7 Usage Notes When using the A/D converter, note the following points. 20.7.
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20.7.3 Access Size and Read Data Table 20.6 shows the relationship between access size and read data. Note the read data obtained with different access sizes, bus widths, and endian modes. The case is shown here in which H'3FF is obtained when AV CC is input as an analog input. FF is the data containing the upper 8 bits of the conversion result, and C0 is the data containing the lower 2 bits. AVCC 100 Ω * 0.1 µF SH7709S AN0 to AN7 AVSS Note: * 10 µF 0.01 µF Figure 20.
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Table 20.5 Analog Input Pin Ratings Item Min Max Unit Analog input capacitance — 20 pF Allowable signal-source impedance — 5 kΩ Table 20.6 Relationship between Access Size and Read Data Bus Width 32 Bits (D31–D0) Access Size 16 Bits (D15–D0) 8 Bits (D7–D0) Endian Little Big Little FFFFFFFF FFFFFFFF FFFF FFFF FF FF C0C0C0C0 C0C0C0C0 C0C0 C0C0 C0 C0 MOV.L#ADDRAH,R9 MOV.W@R9,R8 FFxxFFxx FFxxFFxx FFxx FFxx FF xx xx FF MOV.L#ADDRAL,R9 MOV.
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Section 21 D/A Converter 21.1 Overview The SH7709S includes a D/A converter with two channels. 21.1.1 Features D/A converter features are listed below. • Eight-bit resolution • Two output channels • Conversion time: maximum 10 µs (with 20-pF capacitive load) • Output voltage: 0 V to AVcc 21.1.2 Block Diagram Module data bus Bus interface Figure 21.1 shows a block diagram of the D/A converter.
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21.1.3 I/O Pins Table 21.1 summarizes the D/A converter’s input and output pins. Table 21.1 D/A Converter Pins Pin Name Abbreviation I/O Function Analog power supply pin AVcc Input Analog power supply Analog ground pin AVss Input Analog ground and reference voltage Analog output pin 0 DA0 Output Analog output, channel 0 Analog output pin 1 DA1 Output Analog output, channel 1 21.1.4 Register Configuration Table 21.2 summarizes the D/A converter’s registers. Table 21.
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21.2 Register Descriptions 21.2.1 D/A Data Registers 0 and 1 (DADR0/1) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the data to be converted. When analog output is enabled, the D/A data register values are constantly converted and output at the analog output pins. The D/A data registers are initialized to H'00 by a reset. 21.2.
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Bit 5—D/A Enable (DAE): Controls D/A conversion, together with bits DAOE0 and DAOE1. When the DAE bit is cleared to 0, D/A conversion is controlled independently in channels 0 and 1. When the chip enters standby mode while D/A conversion is enabled, the D/A output is held and the analog power-supply current is equivalent to that during D/A conversion. To reduce the analog power-supply current in standby mode, clear the DAOE0 and DAOE1 bits and disable the D/A output.
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21.3 Operation The D/A converter has two built-in D/A conversion circuits that can perform conversion independently. D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value is modified, conversion of the new data begins immediately. The conversion results are output when bits DAOE0 and DAOE1 are set to 1. An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 21.2. 1. Data to be converted is written in DADR0. 2.
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Rev. 5.
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Section 22 User Debugging Interface (UDI) 22.1 Overview This LSI incorporates a User debugging interface (UDI) and advanced user debugger (AUD) for program debugging. 22.2 User Debugging Interface (UDI) The UDI (User debugging interface) performs on-chip debugging which is supported by this LSI. The UDI described here is a serial interface which is compatible with JTAG (Joint Test Action Group, IEEE Standard 1149.1 and IEEE Standard Test Access Port and Boundary-Scan Architecture) specifications.
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mode, boundary scan and emulator functions can be used. The input level at the ASEMD0 pin should be held for at least one cycle after RESETP negation. ASEBRKAK: KAK Dedicated emulator pin 22.2.2 Block Diagram Figure 22.1 shows a block diagram of the UDI. TDO Shift register SDBPR SDBSR TDI SDIR MUX TCK TMS TAP controller Decoder TRST Figure 22.1 Block Diagram of UDI 22.3 Register Descriptions The UDI has the following registers.
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Table 22.1 shows the UDI register configuration. Table 22.1 UDI Registers CPU Side UDI Side Name Abbreviation R/W Size Address R/W Size Initial Value* Bypass register SDBPR — — — R/W 1 Undefined Instruction register SDIR R 16 H'04000200 R/W 16 H'FFFF Boundary register SDBSR — — — R/W — Undefined Note: * Initialized when TRST pin is low or when TAP is in the test-logic-reset state. 22.3.
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Table 22.2 UDI Commands Bit 15 to 12 TI3 TI2 TI1 TI0 Description 0 0 0 0 EXTEST 0 1 0 0 SAMPLE/PRELOAD 0 1 0 1 Reserved 0 1 1 0 UDI reset negate 0 1 1 1 UDI reset assert 1 0 0 — Reserved 1 0 1 — UDI interrupt 1 1 0 — Reserved 1 1 1 0 Reserved 1 1 1 1 Bypass mode 0 0 0 1 Recovery from sleep (Initial value) Bits 11 to 0—Reserved: These bits are always read as 1. 22.3.
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Table 22.
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Bit Pin Name I/O Bit Pin Name I/O 277 D10 OUT 247 D12 Control 276 D9 OUT 246 D11 Control 275 D8 OUT 245 D10 Control 274 D7 OUT 244 D9 Control 273 D6 OUT 243 D8 Control 272 D5 OUT 242 D7 Control 271 D4 OUT 241 D6 Control 270 D3 OUT 240 D5 Control 269 D2 OUT 239 D4 Control 268 D1 OUT 238 D3 Control 267 D0 OUT 237 D2 Control 266 D31/PTB7 Control 236 D1 Control 265 D30/PTB6 Control 235 D0 Control 264 D29/PTB5 Control 234 BS/
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Bit Pin Name I/O Bit Pin Name I/O 217 A7 OUT 187 CS4/PTK2 OUT 216 A8 OUT 186 CS5/CE1A/PTK3 OUT 215 A9 OUT 185 CS6/CE1B OUT 214 A10 OUT 184 CE2A/PTE4 OUT 213 A11 OUT 183 CE2B/PTE5 OUT 212 A12 OUT 182 A0 Control 211 A13 OUT 181 A1 Control 210 A14 OUT 180 A2 Control 209 A15 OUT 179 A3 Control 208 A16 OUT 178 A4 Control 207 A17 OUT 177 A5 Control 206 A18 OUT 176 A6 Control 205 A19 OUT 175 A7 Control 204 A20 OUT 174 A8 Contr
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Bit Pin Name I/O Bit Pin Name I/O 157 A25 Control 127 BREQ IN 156 BS/PTK4 Control 126 WAIT IN 155 RD Control 125 AUDCK/PTH6 IN 154 WE0/DQMLL Control 124 IOIS16/PTG7 IN 153 WE1/DQMLU/WE Control 123 ASEBRKAK/PTG5 IN 152 WE2/DQMUL/ICIORD/ PTK6 Control 122 CKIO2/PTG4 IN 151 WE3/DQMUU/ICIOWR/ PTK7 Control 121 AUDATA3/PTG3 IN 150 RD/WR Control 120 AUDATA2/PTG2 IN 149 AUDSYNC/PTE7 Control 119 AUDATA1/PTG1 IN 148 CS0/MCS0 Control 118 AUDATA0/PTG0 IN
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Bit Pin Name I/O Bit Pin Name I/O 97 ASEBRKAK/PTG5 OUT 65 RxD2/SCPT4 IN 96 AUDATA3/PTG3 OUT 64 WAKEUP/PTD3 IN 95 AUDATA2/PTG2 OUT 63 RESETOUT/PTD2 IN 94 AUDATA1/PTG1 OUT 62 DRAK0/PTD1 IN 93 AUDATA0/PTG0 OUT 61 DRAK1/PTD0 IN 92 CKE/PTK5 Control 60 DREQ0/PTD4 IN 91 RAS3L/PTJ0 Control 59 DREQ1/PTD6 IN 90 PTJ1 Control 58 RxD1/SCPT2 IN 89 CASL/PTJ2 Control 57 CTS2/IRQ5/SCPT7 IN 88 CASU/PTJ3 Control 56 MCS7/PTC7/PINT7 IN 87 PTJ4 Control 55 MCS6
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Bit Pin Name I/O Bit Pin Name I/O 33 MCS6/PTC6/PINT6 OUT 15 SCK1/SCPT3 Control 32 MCS5/PTC5/PINT5 OUT 14 TxD2/SCPT4 Control 31 MCS4/PTC4/PINT4 OUT 13 SCK2/SCPT5 Control 30 WAKEUP/PTD3 OUT 12 RTS2/SCPT6 Control 29 RESETOUT/PTD2 OUT 11 MCS7/PTC7/PINT7 Control 28 MCS3/PTC3/PINT3 OUT 10 MCS6/PTC6/PINT6 Control 27 MCS2/PTC2/PINT2 OUT 9 MCS5/PTC5/PINT5 Control 26 MCS1/PTC1/PINT1 OUT 8 MCS4/PTC4/PINT4 Control 25 MCS0/PTC0/PINT0 OUT 7 WAKEUP/PTD3 Control 2
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22.4 UDI Operation 22.4.1 TAP Controller Figure 22.2 shows the internal states of the TAP controller. State transitions basically conform with the JTAG standard. 1 Test-logic-reset 0 Run-test/idle 0 1 1 1 Select-DR-scan Select-IR-scan 0 1 1 Capture-DR 0 Shift-DR 1 Capture-IR 0 0 Shift-IR 1 Exit1-DR 0 Pause-DR 1 0 0 Exit1-IR 0 0 Pause-IR 1 0 0 Exit2-DR 1 Exit2-IR 1 Update-DR 1 0 Update-IR 1 0 Figure 22.
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22.4.2 Reset Configuration Table 22.4 Reset Configuration ASEM ASEMD0 * RESET ESETP TRST Chip State High-level Low-level Low-level Normal reset and UDI reset High-level Normal reset Low-level UDI reset only High-level Normal operation 2 Reset hold* 1 High-level Low-level Low-level High-level Low-level High-level 3 ASE user mode* : Normal reset 3 ASE break mode* : RESETP assertion masked Low-level UDI reset only High-level Normal operation Notes: 1.
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22.4.3 UDI Reset An UDI reset is executed by setting an UDI reset assert command in SDIR. An UDI reset is of the same kind as a power-on reset. An UDI reset is released by inputting an UDI reset negate command. SDIR UDI reset assert UDI reset negate Chip internal reset CPU state Branch to H'A0000000 Figure 22.3 UDI Reset 22.4.4 UDI Interrupt The UDI interrupt function generates an interrupt by setting a command from the UDI in the SDIR.
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22.5 Boundary Scan A command can be set in SDIR by the UDI to place the UDI pins in the boundary scan mode stipulated by JTAG. 22.5.1 Supported Instructions This LSI supports the three essential instructions defined in the JTAG standard (BYPASS, SAMPLE/PRELOAD, and EXTEST). BYPASS: The BYPASS instruction is an essential standard instruction that operates the bypass register. This instruction shortens the shift path to speed up serial data transfer involving other chips on the printed circuit board.
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Data loaded into the output pin boundary scan register in the Capture-DR state is not used for external circuit testing (it is replaced by a shift operation). The instruction code is 0000. 22.5.2 Points for Attention 1. Boundary scan mode covers clock-related signals (EXTAL, EXTAL2, XTAL, XTAL2, CKIO). 2. Boundary scan mode does not cover reset-related signals (RESETP, RESETM, CA). 3. Boundary scan mode does not cover UDI-related signals (TCK, TDI, TDO, TMS, TRST). 4.
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Rev. 5.
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Section 23 Electrical Characteristics 23.1 Absolute Maximum Ratings Table 23.1 shows the absolute maximum ratings. Table 23.1 Absolute Maximum Ratings Item Symbol Rating Unit Power supply voltage (I/O) VccQ –0.3 to 4.2 V Power supply voltage (internal) Vcc Vcc – PLL1 Vcc – PLL2 Vcc – RTC –0.3 to 2.5 V Input voltage (except port L) Vin –0.3 to VccQ + 0.3 V Input voltage (port L) Vin –0.3 to AVcc + 0.3 V Analog power-supply voltage AVcc –0.3 to 4.6 V Analog input voltage VAN –0.
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(Max. 1 ms) 3.3 V 3.3 V power 1.7 V/1.8 V/1.9 V/2.0 V 1.7 V/1.8 V/1.9 V/2.0 V power RESETP Pin states undefined All other pins* Pin states undefined Power-on reset state Note: * Except power/GND, clock related, and analog pins Power-On Sequence • Power-off order 1. In the reverse order of powering-on, first turn off the 1.7 V/1.8 V/1.9 V/2.0 V power, then turn off the 3.3 V power within 1 ms. This interval should be as short as possible. 2. Pin states are undefined while only the 1.7 V/1.8 V/1.9 V/2.
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23.2 DC Characteristics Tables 23.2 and 23.3 list DC characteristics. Table 23.2 DC Characteristics Ta = –20 to 75°C Item Symbol Min Typ Max Unit Power supply voltage VccQ 3.0 3.3 3.6 V Vcc, 1.85 2.00 2.15 200 MHz model* Vcc-PLL1, 1.75 1.90 2.05 167 MHz model Vcc-PLL2, 1.65 1.80 2.05 133 MHz model Vcc-RTC 1.55 1.70 1.95 100 MHz model — 410 680 330 540 Vcc = 1.9 V, Iφ = 167 MHz — 250 410 Vcc = 1.8 V, Iφ = 133 MHz — 190 310 Vcc = 1.
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Item Symbol Min Typ Max VccQ × 0.9 — VccQ + V 0.3 EXTAL2 — — — Port L 2.0 — AVcc + 0.3 Other input pins 2.0 — VccQ + 0.3 Input high RESETP, VIH voltage RESETM, NMI, IRQ5 to IRQ0, MD5 to MD0, IRL3 to IRL0, IRLS3 to IRLS0, PINT15 to PINT0, ASEMD0, ADTRG, TRST, EXTAL, CKIO, RxD1, CA Rev. 5.00, 09/03, page 660 of 760 Unit Measurement Conditions When not connecting to a crystal oscillator, connect to Vcc.
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Item Symbol Min Typ Max Unit –0.3 — VccQ × 0.1 V EXTAL2 — — — Port L –0.3 — AVcc × 0.2 Other input pins –0.3 — VccQ × 0.2 Input leak All input pins I Iin I current — — 1.0 µA Vin = 0.5 to VccQ–0.5 V ThreeI/O, all state leak output pins current (off condition) I Isti I — — 1.0 µA Vin = 0.5 to VccQ–0.5 V Output high voltage VOH 2.4 — — V VccQ = 3.0 V, IOH = –200 µA 2.0 — — VccQ = 3.0 V, IOH = –2 mA VccQ = 3.6 V, IOL = 1.
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Item Symbol Min Typ Max Unit Analog powersupply voltage AVcc 3.0 3.3 3.6 V AIcc — 0.8 2 mA Analog powersupply During A/D conversion current During A/D and D/A conversion — 2.4 6 mA Idle — 1 20 µA Measurement Conditions Ta = 25°C Notes: Even when PLL is not used, always connect Vcc-PLL1 and Vcc-PLL2 to Vcc and connect Vss-PLL1 and Vss-PLL2 to Vss. Even when RTC is not used, always supply power between Vcc-RTC and Vss-RTC. AVcc must be under condition of VccQ – 0.
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23.3 AC Characteristics In general, inputting for this LSI should be clock synchronous. Keep the setup and hold times for each input signal unless otherwise specified. Table 23.4 Operating Frequency Range VccQ = 3.3 ± 0.3 V, VccQ = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C Item Operating frequency CPU, cache, TLB Symbol Min Typ Max Unit Remarks f 30 — 200 MHz 200 MHz model 25 External bus 30 — 167 167 MHz model 133 133 MHz model 100 100 MHz model 66.
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23.3.1 Clock Timing Table 23.5 Clock Timing VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C Item Symbol Min Max Unit Figure EXTAL clock input frequency (clock mode 0) fEX 25 66.67 MHz 23.1 EXTAL clock input cycle time (clock mode 0) tEXcyc 15 40 ns EXTAL clock input frequency (clock mode 1) fEX 6.25 16.67 MHz EXTAL clock input cycle time (clock mode 2) tEXcyc 60 160 ns EXTAL clock input low pulse width tEXL 1.
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tEXcyc tEXH EXTAL* (input) 1/2 VCCQ tEXL VIH VIH 1/2 VCCQ VIH VIL VIL tEXF tEXR Note: * The clock input from the EXTAL pin. Figure 23.1 EXTAL Clock Input Timing tCKIcyc tCKIH CKIO (input) 1/2 VCCQ tCKIL VIH VIH VIH 1/2 VCCQ VIL VIL tCKIR tCKIF Figure 23.2 CKIO Clock Input Timing tcyc tCKOH CKIO (output) 1/2VCCQ VOH tCKOL VOH VOH VOL VOL tCKOF tCK2D CKIO2 (output) VOH 1/2VCCQ tCKOR tCK2D VOH VOH VOL VOL tCK2OF tCK2OR Figure 23.3 CKIO Clock Output Timing Rev. 5.
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Stable oscillation CKIO, internal clock VCC VCC min tRESPW tOSC1 tRESPS RESETP Note: Oscillation settling time when built-in oscillator is used Figure 23.4 Power-on Oscillation Settling Time Stable oscillation Standby CKIO, internal clock tOSC2 tRESPW/MW tRESPS/MS RESETP RESETM Note: Oscillation settling time when built-in oscillator is used in the oscillation off mode Figure 23.5 Oscillation Settling Time at Standby Return (Return by Reset) Rev. 5.
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Standby Stable oscillation CKIO, internal clock tOSC3 NMI WAKEUP Note: Oscillation settling time when built-in oscillator is used in the oscillation off mode Figure 23.6 Oscillation Settling Time at Standby Return (Return by NMI) Standby Stable oscillation CKIO, internal clock tOSC4 IRL3 to IRL0 IRQ4 to IRQ0 PINT0/1 WAKEUP Note: Oscillation settling time when built-in oscillator is used in the oscillation off mode (only when RTC is used) Figure 23.
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Reset or NMI interrupt request Stable input clock Stable input clock EXTAL input or CKIO input PLL synchronization tPLL1 PLL synchronization PLL output, CKIO output Internal clock STATUS 0 STATUS 1 Normal Standby Normal Note: PLL oscillation settling time during the continued oscillation mode or when clock is input from EXTAL pin or CKIO pin Figure 23.
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Multiplication rate modified EXTAL input*1 (CKIO input) tPLL2 CKIO output*2 (PLL output) Internal clock Notes: 1. CKIO input in clock mode 7 2. PLL output in other than clock mode 7 Figure 23.10 PLL Synchronization Settling Time when Frequency Multiplication Rate Modified Rev. 5.
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23.3.2 Control Signal Timing Table 23.6 Control Signal Timing Vcc = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C Item Symbol Min Max Unit Figure — tcyc 23.11, 23.
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CKIO tRESPS/MS tRESPS/MS tRESPW/MW RESETP RESETM Figure 23.11 Reset Input Timing CKIO tRESPH/MH tRESPS/MS VIH RESETP RESETM VIL tNMIH tNMIS VIH NMI VIL tIRQH tIRQS VIH IRQ5 to IRQ0 VIL Figure 23.12 Interrupt Signal Input Timing CKIO tIRQOD tIRQOD IRQOUT Figure 23.13 IRQOUT QOUT Timing Rev. 5.
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CKIO tBREQH tBREQS tBREQH tBREQS BREQ tBACKD tBACKD BACK RD, RD/WR, RAS, CAS, CSn, WEn, BS, MCSn tBOFF2 tBON2 tBOFF1 tBON1 A25 to A0, D31 to D0 Figure 23.14 Bus Release Timing Normal mode Standby mode Normal mode CKIO tSTD tSTD tBOFF2 tBON2 tBOFF1 tBON1 STATUS 0 STATUS 1 RD, RD/WR, RAS, CAS, CSn, WEn, BS, MCSn A25 to A0, D31 to D0 Figure 23.15 Pin Drive Timing at Standby Rev. 5.
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23.3.3 AC Bus Timing Table 23.7 Bus Timing Clock Modes 0/1/2/7, VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C Item Symbol Min Max Unit Figure Address delay time tAD 1.5 12 ns 23.16–23.36, 23.39–23.46 Address setup time 1 Address hold time* tAS 0 — ns 23.16–23.18 tAH 4 — ns 23.16–23.21 BS delay time tBSD — 10 ns 23.16–23.36, 23.40–23.46 CS delay time 1 tCSD1 0 10 ns 23.16–23.21, 23.40–23.46 CS delay time 2 tCSD2 — 10 ns 23.16–23.
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Item Symbol Min Max Unit Figure ICIORD delay time tICRSD — 10 ns 23.44–23.46 ICIOWR delay time tICWSD — 10 ns 23.44–23.46 IOIS16 setup time tIO16S 6 — ns 23.45, 23.46 IOIS16 hold time tIO16H 4 — ns 23.45, 23.46 DACK delay time 1 tDAKD1 (Reference for CKIO rise) — 10 ns 23.16–23.36, 23.39–23.46 DACK delay time 2 tDAKD2 (Reference for CKIO fall) — 10 ns 23.16–23.22 Notes: 1. Specified based on the slowest negate timing for CSn, RD, or WEn 2.
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23.3.4 Basic Timing T1 T2 CKIO tAD tAD tAS A25 to A0 tAH tCSD1 tRWH tCSD2 CSn tRDH1 tRWD tRWD RD/WR tAH tRSD tRSD tRWH RD (read) tRDH1 tRDS1 D31 to D0 (read) tAH tWED tRWH tWED WEn (write) tWDH3 tWDD1 tWDH1 D31 to D0 (write) tBSD tBSD BS tDAKD1 tDAKD1 DACKn Figure 23.16 Basic Bus Cycle (No Wait) Rev. 5.
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T1 Tw T2 CKIO tAD tAD tAS A25 to A0 tAH tCSD2 tCSD1 tRWH CSn tRDH1 tRWD tRWD RD/WR tAH tRSD tRWH tRSD RD (read) tRDH1 tRDS1 D31 to D0 (read) tWED tAH tWED tRWH WEn (write) tWDH3 tWDD1 tWDH1 D31 to D0 (write) tBSD tBSD BS tDAKD1 tDAKD1 DACKn tWTS tWTH WAIT Figure 23.17 Basic Bus Cycle (One Wait) Rev. 5.
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T1 Tw Tw T2 CKIO tAD tAS tAD A25 to A0 tAH tCSD1 tCSD2 tRWH CSn tRDH1 tRWD tRWD RD/WR tAH tRSD tRSD RD (read) tRWH tRDH1 tRDS1 D31 to D0 (read) tAH tWED tWED WEn (write) tRWH tWDH3 tWDD1 tWDH1 D31 to D0 (write) tBSD tBSD BS tDAKD2 tDAKD1 DACKn tWTS tWTH tWTS tWTH WAIT Figure 23.18 Basic Bus Cycle (External Wait, WAITSEL = 1) Rev. 5.
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23.3.5 Burst ROM Timing T1 TB2 TB1 TB2 TB1 TB2 TB1 T2 CKIO tAD tAD A25 to A4 tAD tAD A3 to A0 tAH tCSD2 tCSD1 tRWH CSn tRDH1 tRWD tRWD RD/WR tAH tRSD tRSD tRSD tAH tRSD tRWH RD tRDH1 tRDH1 tRDS tRDS1 D31 to D0 tBSD tBSD tBSD tBSD BS tDAKD1 tDAKD2 DACKn tWTS tWTH tWTS tWTH tWTS tWTH WAIT Note: In the write cycle, the basic bus cycle, the basic bus cycle is performed. Figure 23.19 Burst ROM Bus Cycle (No Wait) Rev. 5.
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T1 Tw Tw TB2 TB1 Tw TB2 T2 T2 CKIO tAD tAD A25 to A4 tAD A3 to A0 tAH tCSD2 tCSD1 tRWH CSn tRDH1 tRWD tRWD RD/WE tAH tRSD tRSD tAH tRSD tRSD tRSD tRWH RD tRDH1 tRDH1 tRDS1 tRDH1 tRDS1 D31 to D0 tBSD tBSD tBSD tBSD BS tDAKD1 tDAKD2 DACKn tWTS tWTH tWTS tWTH WAIT Note: In the write cycle, the basic bus cycle is performed. Figure 23.20 Burst ROM Bus Cycle (Two Waits) Rev. 5.
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T1 Tw Tw TB2 TB1 TBw T2 CKIO tAD tAD A25 to A4 tAD A3 to A0 tAH tCSD2 tCSD1 tRWH CSn tRDH1 tRWD tRWD RD/WR tAH tRSD tRSD1 tAH tRSD1 tRSD tRWH RD tRDH1 tRDH1 tRDS1 tRDS D31 to D0 tBSD tBSD tBSD tBSD BS tDAKD2 tDAKD1 DACKn tWTS tWTH tWTS tWTH tWTS tWTH tWTS tWTH WAIT Note: In the write cycle, the basic bus cycle is performed. Figure 23.21 Burst ROM Bus Cycle (External Wait, WAITSEL = 1) Rev. 5.
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23.3.6 Synchronous DRAM Timing Tc1 Tr (Tpc) Tc2 CKIO tAD tAD Row address A25 to A16 tAD A12 or A10 tAD A15 to A0 Read A command Row address tAD tAD tAD Row address tAD Column address tCSD3 tCSD3 tRWD tRWD CSn RD/WR tRASD2 tRASD2 RAS tCASD2 tCASD2 CAS tDQMD tDQMD DQMxx tRDS2 tRDH2 D31 to D0 tBSD tBSD BS CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.22 Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0) Rev. 5.
PAGE 726
Tr Trw Trw Tc1 Tcw Td1 (Tpc) (Tpc) CKIO tAD tAD A25 to A16 Row address tAD A12 or A10 tAD Read A command Row address tAD tAD Row address A15 to A0 tAD tAD Column address tCSD3 tCSD3 tRWD tRWD CSn RD/WR tRASD2 tRASD2 RAS tCASD2 tCASD2 CAS tDQMD tDQMD DQMxx tRDS2 tRDH2 D31 to D0 tBSD tBSD BS CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.23 Synchronous DRAM Read Bus Cycle (RCD = 2, CAS Latency = 2, TPC = 1) Rev. 5.
PAGE 727
Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 (Tpc) (Tpc) CKIO tAD tAD Row address A25 to A16 tAD tAD Row address A12 or A10 tAD A15 to A0 tAD Read command tAD Row address tAD Read A command tAD Column address (1-4) tCSD3 tCSD3 tRWD tRWD CSn RD/WR tRASD2 tRASD2 RAS tCASD2 tCASD2 CAS tDQMD tDQMD DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.
PAGE 728
Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 (Tpc) CKIO tAD A25 to A16 tAD Row address tAD A12 or A10 tAD tAD Row address tAD Read command tAD A15 to A0 Row address tAD tAD tAD Column address (1-4) tCSD3 tCSD3 CSn tRWD tRWD RD/WR tRASD2 tRASD2 RAS tCASD2 tCASD2 CAS tDQMD tDQMD DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 (read) tBSD tBSD BS CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.
PAGE 729
Tc1 Tr (Trwl) (Tpc) CKIO tAD A25 to A16 tAD Row address tAD A12 or A10 tAD Row address Write A command tAD tAD Row address A15 to A0 tAD tAD Column address tCSD3 tCSD3 CSn tRWD tRWD tRASD2 tRASD2 tRWD RD/WR RAS tCASD2 tCASD2 tDQMD tDQMD tWDD2 tWDH2 tBSD tBSD CAS DQMxx D31 to D0 BS (High) CKE tDAKD1 tDAKD1 DACKn Figure 23.26 Synchronous DRAM Write Bus Cycle (RCD = 0, TPC = 0, TRWL = 0) Rev. 5.
PAGE 730
Trw Tr Trw Tc1 (Trwl) (Trwl) (Tpc) (Tpc) CKIO tAD A25 to A16 tAD Row address tAD A12 or A10 A15 to A0 tAD tAD tAD Write A command Row address tAD tAD tAD tAD Column address Row address tCSD1 tCSD1 CSn tRWD tRWD tRWD tCASD2 tCASD2 tDQMD tDQMD tWDD2 tWDH2 tBSD tBSD RD/WR tRASD2 tRASD2 RAS CAS DQMxx D31 to D0 BS (High) CKE tDAKD1 tDAKD1 DACKn Figure 23.27 Synchronous DRAM Write Bus Cycle (RCD = 2, TPC = 1, TRWL = 1) Rev. 5.
PAGE 731
Tr Tc1 Tc2 Tc3 Tc4 (Trwl) (Tpc) (Tpc) CKIO tAD A25 to A16 tAD Row address tAD A12 or A10 A15 to A0 tAD Row address tAD tAD tAD Write command tAD Write A command tAD Row address Column address (1-4) tCSD3 tCSD3 CSn tRWD tRWD tRWD tRASD2 tRASD2 RD/WR RAS tCASD2 tCASD2 tDQMD tDQMD CAS DQMxx tWDD2 tWDD2 tWDH2 D31 to D0 tBSD tBSD BS (High) CKE tDAKD1 tDAKD1 DACKn Figure 23.
PAGE 732
Tr Trw Tc1 Tc2 Td4 Tc3 (Trwl) (Tpc) CKIO tAD tAD Row address A25 to A16 tAD A12 or A10 A15 to A0 tAD tAD Row address tAD tAD Write command tAD Write A command tAD Row address tCSD3 Column address (1-4) tCSD3 CSn tRWD tRWD tRWD tCASD2 tCASD2 tDQMD tDQMD RD/WR tRASD2 tRASD2 RAS CAS DQMxx tWDD2 tWDD2 tWDH2 D31 to D0 tBSD tBSD BS CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.29 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write × 4), RCD = 1, TPC = 0, TRWL = 0) Rev.
PAGE 733
Tnop Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 CKIO tAD tAD A25 to A16 Row address tAD tAD Read command A12 or A10 tAD tAD Column address A15 to A0 tCSD3 tCSD3 tRWD tRWD CSn RD/WR tRASD2 RAS tCASD2 tCASD2 CAS tDQMD tDQMD DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.30 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Latency = 1) Rev. 5.
PAGE 734
Tc1 Tc2 Tc3/Td1 Tc4/Td2 Td3 Td4 CKIO tAD tAD A25 to A16 Row address tAD tAD Read command A12 or A10 tAD tAD A15 to A0 Column address tCSD3 tCSD3 tRWD tRWD CSn RD/WR tRASD2 RAS tCASD2 tCASD2 CAS tDQMD tDQMD DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.31 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Latency = 2) Rev. 5.
PAGE 735
Tr Tp Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 CKIO tAD tAD Row address A25 to A16 tAD tAD tAD tAD Row address A12 or A10 tAD Read command tAD tAD Row address A15 to A0 Column address tCSD3 tCSD3 CSn tRWD tRWD tRWD RD/WR tRASD2 tRASD2 RAS tCASD2 tCASD2 CAS tDQMD tDQMD tDQMD DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.
PAGE 736
Tp Tpw Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 CKIO tAD tAD Row address A25 to A16 tAD tAD tAD tAD Row address A12 or A10 tAD Read command tAD tAD Row address A15 to A0 Column address tCSD3 tCSD3 CSn tRWD tRWD tRASD2 tRASD2 tRWD RD/WR tRASD2 tRASD2 RAS tCASD2 tCASD2 CAS tDQMD tDQMD tDQMD DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.
PAGE 737
Tc1 Tc2 Tc3 Tc4 CKIO tAD tAD Row address A25 to A16 tAD tAD Write command A12 or A10 tAD tAD Column address A15 to A0 tCSD3 tCSD3 tRWD tRWD tRASD2 tRASD2 tCASD2 tCASD2 tDQMD tDQMD tWDD2 tWDD2 tBSD tBSD CSn RD/WR RAS CAS DQMxx D31 to D0 BS CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.34 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Same Row Address) Rev. 5.
PAGE 738
Tr Tp Tc1 Tc2 Tc3 Tc4 CKIO tAD tAD Row address A25 to A16 tAD tAD Row address A12 or A10 tAD Write command tAD Row address A15 to A0 tAD tAD tCSD3 tAD Column address tCSD3 CSn tRWD tRWD tRWD tRWD RD/WR tRASD2 tRASD2 RAS tCASD2 tCASD2 tDQMD tDQMD tWDD2 tWDD2 tBSD tBSD CAS tDQMD DQMxx D31 to D0 BS CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.35 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row Address, TPC = 0, RCD = 0) Rev. 5.
PAGE 739
Tp Tpw Tr Trw Tc1 Tc2 Tc3 Td4 CKIO tAD tAD Row address A25 to A16 tAD tAD tAD tAD Row address A12 or A10 tAD tAD Write command tAD Row address A15 to A0 tAD Column address tCSD3 tCSD3 CSn tRWD tRWD tRASD2 tRASD2 tRWD tRWD tCASD2 tCASD2 tDQMD tDQMD tWDD2 tWDD2 tBSD tBSD RD/WR tRASD2 tRASD2 RAS CAS tDQMD DQMxx D31 to D0 BS CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.36 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row Address, TPC = 1, RCD = 1) Rev.
PAGE 740
Tp Tpc TRr TRrw TRrw (Tpc) (Tpc) CKIO CKE (High) tCSD3 tCSD3 tCSD3 tCSD3 tRASD2 tRASD2 tRASD2 tRASD2 tCASD2 tCASD2 CSn RAS3x CASxx tRWD tRWD RD/WR Figure 23.37 Synchronous DRAM Auto-Refresh Timing (TRAS = 1, TPC = 1) Rev. 5.
PAGE 741
Tp Tpc TRa1 (TRs2) (TRs2) TRs3 (Tpc) (Tpc) CKIO t CKED t CKED CKE t CSD3 t CSD3 t CSD3 t CSD3 CSn t RASD2 t RASD2 t RASD2 t RASD2 RAS t CASD2 t CASD2 CAS t RWD t RWD t RWD RD/WR Figure 23.38 Synchronous DRAM Self-Refresh Cycle (TRAS = 1, TPC = 1) Rev. 5.
PAGE 742
TRp2 TRp1 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 CKIO tAD tAD tAD tAD tAD tAD tAD tAD tAD A13 or A11 tAD tAD A12 or A10 A11 to A2 or A9 to A2 tCSD3 tCSD3 CSn tRWD tRWD tRWD tRASD2 tRASD2 RD/WR tRASD2 tRASD2 tCASD2 tCASD2 RAS CASxx D31 to D0 CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.39 Synchronous DRAM Mode Register Write Cycle Rev. 5.
PAGE 743
23.3.7 PCMCIA Timing Tpcm1 Tpcm2 CKIO tAD tAD tCSD1 tCSD1 tRWD tRWD A25 to A0 CExx RD/WR tRSD tRSD RD (read) tRDH1 tRDS1 D15 to D0 (read) tWED tWED WE1 (write) tWDH4 tWDH1 tWDD1 D15 to D0 (write) tBSD tBSD BS tDAKD1 tDAKD1 DACKn Figure 23.40 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) Rev. 5.
PAGE 744
Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO tAD tAD tCSD1 tCSD1 tRWD tRWD A25 to A0 CExx RD/WR tRSD tRSD RD (read) tRDH1 tRDS1 D15 to D0 (read) tWED tWED WE1 (write) tWDH4 tWDD1 tWDH1 D15 to D0 (write) tBSD tBSD BS tDAKD1 tDAKD1 DACKn tWTS tWTH tWTS tWTH WAIT Figure 23.41 PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait, WAITSEL = 1) Rev. 5.
PAGE 745
Tpcm1 Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2 CKIO tAD tAD A25 to A4 tAD tAD tAD tAD A3 to A0 tCSD1 tCSD1 tRWD tRWD CExx RD/WR tRSD tRSD RD (read) tRSD tRSD tRDH1 tRDS1 tRDH1 tRDS1 D15 to D0 (read) tBSD tBSD tBSD tBSD BS tDAKD1 tDAKD1 DACKn Note: Even though burst mode is set, write cycle operation is the same as in normal mode. Figure 23.42 PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait) Rev. 5.
PAGE 746
Tpcm0 Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm2 Tpcm2w CKIO tAD tAD A25 to A4 tAD tAD tAD A3 to A0 tCSD1 tCSD1 tRWD tRWD CExx RD/WR tRSD tRSD RD (read) tRSD tRSD tRDH1 tRDH1 tRDS1 tRDS1 D15 to D0 (read) tBSD tBSD tBSD tBSD BS tDAKD1 tDAKD1 DACKn tWTS tWTH tWTS tWTH tWTS tWTH WAIT Note: Even though burst mode is set, the write cycle operation is the same as in normal mode. Figure 23.
PAGE 747
Tpci1 Tpci2 CKIO tAD tAD tCSD1 tCSD1 tRWD tRWD A25 to A0 CExx RD/WR tICRSD tICRSD ICIORD (read) tRDH1 tRDS1 D15 to D0 (read) tICWSD tICWSD ICIOWR (write) tWDH4 tWDH1 tWDD1 D15 to D0 (write) tBSD tBSD BS tDAKD1 tDAKD1 DACKn Figure 23.44 PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait) Rev. 5.
PAGE 748
Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w CKIO tAD tAD tCSD1 tCSD1 tRWD tRWD A25 to A0 CExx RD/WR tICRSD tICRSD ICIORD (read) tRDH1 tRDS1 D15 to D0 (read) tICWSD tICWSD ICIOWR (write) tWDH4 tWDH1 tWDD1 D15 to D0 (write) tBSD tBSD BS tDAKD1 tDAKD1 DACKn tWTS tWTH tWTS tWTH WAIT tIO16S tIO16H IOIS16 Figure 23.45 PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait, WAITSEL = 1) Rev. 5.
PAGE 749
Tpci0 Tpci1 Tpci1w Tpci2 Tpci1 Tpci1w Tpci2 Tpci2w CKIO tAD tAD A25 to A4 tAD tAD tAD tCSD1 tCSD1 tCSD1 A0 CExx tRWD tRWD RD/WR tICRSD tICRSD ICIORD (read) tICRSD tICRSD tRDH1 tRDH1 tRDS1 tRDS1 D15 to D0 (read) tICWSD tICWSD tICWSD tICWSD ICIOWR (write) tWDH4 tWDD1 tWDH4 tWDD1 tWDH1 D15 to D0 (write) tBSD tBSD tBSD tBSD BS tDAKD1 tDAKD1 DACKn tWTS tWTH tWTS tWTH WAIT tIO16S tIO16H IOIS16 Figure 23.
PAGE 750
23.3.8 Peripheral Module Signal Timing Table 23.8 Peripheral Module Signal Timing VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C Module Item Symbol Min Max Unit Figure TMU, RTC Timer input setup time tTCLKS 15 — ns 23.47 Timer clock input setup time tTCKS 15 — Timer clock pulse width tTCKWH 1.5 — SCI Port DMAC Edge specification 23.48 Pcyc tTCKWL 2.5 — Oscillation settling time tROSC 3 — s Input clock cycle tSCYC 4 — Pcyc* 23.
PAGE 751
CKIO tTCLKS TCLK (input) Figure 23.47 TCLK Input Timing tTCKS CKIO tTCKS TCLK (input) tTCKWL tTCKWH Figure 23.48 TCLK Clock Input Timing Stable oscillation RTC crystal oscillator VCC VCCmin tROSC Figure 23.49 Oscillation Settling Time at RTC Crystal Oscillator Power-on tSCKW SCK (input) tSCKR tSCKF tSCYC Figure 23.50 SCK Input Clock Timing Rev. 5.
PAGE 752
tSCYC SCK tTXD TxD (data transmissiion) RxD (data reception) tRXS tRXH tCTSS tCTSH tRTSD RTS CTS Figure 23.51 SCI I/O Timing in Clock Synchronous Mode CKIO tPORTS1 tPORTH1 PORT 7 to 0 (read) (B:P clock ratio = 1:1) tPORTS2 tPORTH2 PORT 7 to 0 (read) (B:P clock ratio = 2:1) tPORTS3 tPORTH3 PORT 7 to 0 (read) (B:P clock ratio = 4:1) tPORTD PORT 7 to 0 (write) Figure 23.52 I/O Port Timing CKIO tDREQS tDREQH DREQn Figure 23.53 DREQ Input Timing Rev. 5.
PAGE 753
CKIO tDRAKD tDRAKD DRAK0/1 Figure 23.54 DRAK Output Timing 23.3.9 UDI-Related Pin Timing Table 23.9 UDI-Related Pin Timing VccQ = 3.3 ± 0.3V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3V, Ta = –20 to 75°C Item Symbol Min Max Unit Figure TCK cycle time tTCKCYC 50 — ns 23.
PAGE 754
RESETP tTRSTS tTRSTH TRST Figure 23.56 TRST Input Timing (Reset Hold) TCK tTCKCYC tTDIS tTDIH tTMSS tTMSH TDI TMS tTDOD TDO Figure 23.57 UDI Data Transfer Timing RESETP tASEMD0S tASEMD0H ASEMD0 Figure 23.58 ASEMD0 Input Timing Rev. 5.
PAGE 755
23.3.10 AC Characteristics Measurement Conditions • I/O signal reference level: VccQ/2 (VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V) • Input pulse level: Vss to 3.0 V (where RESETP, RESETM, ASEND0, IRLS3 to IRLS0, IRL3 to IRL0, ADTRG, PINT15 to PINT0, TRST, RxD1, CA, NMI, IRQ5–IRQ0, CKIO, and MD5–MD0 are within Vss to Vcc) • Input rise and fall times: 1 ns IOL DUT output LSI output pin VREF CL IOH Notes: 1. CL is the total value that includes the capacitance of measurement instruments, etc.
PAGE 756
23.3.11 Delay Time Variation Due to Load Capacitance A graph (reference data) of the variation in delay time when a load capacitance greater than that stipulated (30 or 50 pF) is connected to this LSI's pins is shown below. The graph shown in figure 23.60 should be taken into consideration in the design process if the stipulated capacitance is exceeded in connecting an external device. If the connected load capacitance exceeds the range shown in figure 23.60, the graph will not be a straight line.
PAGE 757
23.4 A/D Converter Characteristics Table 23.10 lists the A/D converter characteristics. Table 23.10 A/D Converter Characteristics VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C Item Min Typ Max Unit Resolution 10 10 10 bits Conversion time 15 — — µs Analog input capacitance — — 20 pF Permissible signal-source (singlesource) impedance — — 5 kΩ Nonlinearity error — — ±3.0 LSB Offset error — — ±2.0 LSB Full-scale error — — ±2.
PAGE 758
Rev. 5.
PAGE 759
Appendix A Pin Functions A.1 Pin States Table A.1 shows pin states during resets, power-down states, and the bus-released state. Table A.
PAGE 760
Reset Power-Down Category Pin Address bus A[25:0] Z O Data bus D[15:0] Z D[23:16]/PTA[7:0] Z I 2 IP* D[31:24]/PTB[7:0] Z IP* CS0/MCS0 H O CS[2:4]/PTK[0:2] H CS5/CE1A/PTK[3] H CS6/CE1B H BS/PTK[4] H RAS3L/PTJ[0] H Bus control DMAC Sleep Bus Released ZL* O Z Z 2 ZK* IO 2 IOP* Z 2 ZP* Standby 9 2 2 2 ZP* OP* 2 OP* 2 ZP* 2 ZP* 10 O 2 OP* Z 2 ZP* ZK* 10 ZH* IOP* OP* 2 OP* 2 10 2 ZH* K* 10 2 ZH* K* O 2 OP* ZH* 10 2 ZH* K* O Z 2 2 ZOK* 3 ZOK* 3 OP* 2 O
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Reset Category Pin SCI/Smart card RxD0/SCPT[0] without FIFO TxD0/SCPT[0] Power-Down Power-On Manual Reset Reset 6 Z ZI* Z SCK0/SCPT[1] V RxD1/SCPT[2] Z TxD1/SCPT[2] 6 ZO* 2 ZP* 6 Bus Released Standby Sleep Z 2 ZK* IZ* 5 OZ* IZ* 5 OZ* 2 IOP* 5 IZ* 4 IOP* 5 IZ* 5 OZ* 4 IOP* 5 ZK* 5 4 Z ZI* 6 ZO* Z 2 ZK* SCK1/SCPT[3] V *2 *2 OZ* 4 IOP* SCIF with FIFO RxD2/SCPT[4] Z TxD2/SCPT[4] Z IZ* 5 OZ* IZ* 5 OZ* SCK2/SCPT[5] V ZO* 2 ZP* Z 2 ZK* 2 4 RTS2/SCPT[6] OP* 6 ZI* IOP
PAGE 762
Reset Category Pin Analog AN[5:0]/PTL[5:0] AN[6:7]/DA[1:0]/PTL[6:7] I: O: H: L: Z: P: K: V: Power-Down Power-On Manual Reset Reset 6 Z ZI* Z ZI *6 Standby Sleep Bus Released Z 11 OZ* I 8 IO* I 8 IO* Input Output High-level output Low-level output High impedance Input or output depending on register setting Input pin is high impedance, output pin holds its state I/O buffer off, pull-up MOS on Notes: 1. Depending on the clock mode (MD2–MD0 setting). 2. K or P when the port function is used. 3.
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A.2 Pin Specifications Table A.2 shows the pin specifications. Table A.2 Pin Specifications Pin Pin No. (FP-208C, FP-208E) Pin No.
PAGE 764
Pin Pin No. (FP-208C, FP-208E) Pin No.
PAGE 765
Pin Pin No. (FP-208C, FP-208E) Pin No.
PAGE 766
Pin No. (FP-208C, FP-208E) Pin Pin No.
PAGE 767
Pin No. (FP-208C, FP-208E) Pin Pin No. (BP-240A) I/O Function CKIO 162 A15 I/O System clock I/O XTAL2 4 D1 O Crystal oscillator pin (for on-chip RTC) EXTAL2 5 D3 I Crystal oscillator pin (for on-chip RTC) CKE/PTK[5] 105 T18 I/O CK enable for SDRAM / I/O port CA 194 B7 I VCCQ 21, 35, 47, 59, 71, 85, 97, 111, 163, 183 H4, M1, R1, U3, V8, U15, R19, C17, A10, U12 Power Power supply (3.3 V) supply VCC–RTC 3 E2 Power RTC oscillator power supply supply (2.0/1.9/1.8/1.
PAGE 768
A.3 Treatment of Unused Pins • When RTC is not used  EXTAL2: Pull up (2.0/1.9/1.8/1.7 V)  XTAL2: Leave unconnected  VCC–RTC: Power supply (2.0/1.9/1.8/1.7 V)  VSS–RTC: Power supply (0 V) • When PLL2 is not used  CAP2: Leave unconnected  VCC–PLL2: Power supply (2.0/1.9/1.8/1.7 V)  VSS–PLL2: Power supply (0 V) • When on-chip crystal oscillator is not used  XTAL: Leave unconnected • When EXTAL pin is not used  EXTAL: Pull up (3.
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A.4 Pin States in Access to Each Address Space Table A.
PAGE 770
32-Bit Bus Width Byte Byte Byte Byte Word Word Access Access Access Longword Access Access Access (Address (Address (Address (Address (Address (Address Access 4n) 4n + 1) 4n + 2) 4n + 3) 4n) 4n + 2) Pin CS6 to CS2, CS0 RD RD/WR R Enabled Enabled Enabled Enabled Enabled Enabled Enabled Low Low Low Low Low Low Low W High High High High High High High R High High High High High High High W Low Low Low Low Low Low Low BS Enabled Enabled Enabled Enabled Enabled Enabl
PAGE 771
Table A.
PAGE 772
32-Bit Bus Width Byte Byte Byte Byte Word Word Access Access Access Longword Access Access Access (Address (Address (Address (Address (Address (Address Access 4n) 4n + 1) 4n + 2) 4n + 3) 4n) 4n + 2) Pin CS6 to CS2, CS0 RD RD/WR R Enabled Enabled Enabled Enabled Enabled Enabled Enabled Low Low Low Low Low Low Low W High High High High High High High R High High High High High High High W Low Low Low Low Low Low Low BS Enabled Enabled Enabled Enabled Enabled Enabl
PAGE 773
Table A.
PAGE 774
32-Bit Bus Width Byte Byte Byte Byte Word Word Access Access Access Longword Access Access Access (Address (Address (Address (Address (Address (Address Access 4n) 4n + 1) 4n + 2) 4n + 3) 4n) 4n + 2) Pin CS6 to CS2, CS0 RD RD/WR R Enabled Enabled Enabled Enabled Enabled Enabled Enabled Low Low Low Low Low Low Low W — — — — — — — R High High High High High High — — — — — — High W — BS Enabled Enabled Enabled Enabled Enabled Enabled Enabled RAS3U/PTE[2] High Hig
PAGE 775
Table A.
PAGE 776
32-Bit Bus Width Byte Byte Byte Byte Word Word Access Access Access Longword Access Access Access (Address (Address (Address (Address (Address (Address Access 4n) 4n + 1) 4n + 2) 4n + 3) 4n) 4n + 2) Pin CS6 to CS2, CS0 RD RD/WR R Enabled Enabled Enabled Enabled Enabled Enabled Enabled Low Low Low Low Low Low Low W — — — — — — — R High High High High High High — — — — — — High W — BS Enabled Enabled Enabled Enabled Enabled Enabled Enabled RAS3U/PTE[2] High Hig
PAGE 777
Table A.
PAGE 778
Table A.
PAGE 779
Table A.
PAGE 780
PCMCIA Memory Interface (Area 6) 8-Bit Bus Width Pin CS6 to CS2, CS0 RD RD/WR Byte/ Word/ Longword Access Enabled R Low 16-Bit Bus Width Byte Access (Address 2n) Byte Access (Address 2n + 1) Word/ Longword Access PCMCIA/IO Interface (Area 6) 8-Bit Bus Width Byte/ Word/ Longword Access 16-Bit Bus Width Byte Access (Address 2n) Byte Access (Address 2n+1) Word/ Longword Access Enabled High Enabled Enabled Enabled High Enabled Low Low Low High High High High W High High High High Hig
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Table A.
PAGE 782
PCMCIA Memory Interface (Area 6) 8-Bit Bus Width Pin CS6 to CS2, CS0 RD RD/WR BS Byte/ Word/ Longword Access Enabled PCMCIA/IO Interface (Area 6) 16-Bit Bus Width 8-Bit Bus Width Byte Access (Address 2n + 1) Byte/ Word/ Longword Access Byte Access (Address 2n) Word/ Longword Access 16-Bit Bus Width Byte Access (Address 2n) Byte Access (Address 2n+1) Word/ Longword Access Enabled High Enabled Enabled Enabled High Enabled R Low Low Low Low High High High High W High High High Hi
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Appendix B Memory-Mapped Control Registers B.1 Register Address Map Table B.1 Memory-Mapped Control Registers 1 2 4 Size (Bits) Access Size (Bits)3.
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1 2 Module* Bus* WTCSR CPG I BCR1 BSC BCR2 BSC WCR1 4 Address* 3 Size (Bits) Access Size (Bits)* FFFFFF86 8 16 I FFFFFF60 16 16 I FFFFFF62 16 16 BSC I FFFFFF64 16 16 WCR2 BSC I FFFFFF66 16 16 MCR BSC I FFFFFF68 16 16 PCR BSC I FFFFFF6C 16 16 Control Register RTCSR BSC I FFFFFF6E 16 16 RTCNT BSC I FFFFFF70 16 16 RTCOR BSC I FFFFFF72 16 16 RFCR BSC I FFFFFF74 16 16 SDMR BSC I FFFFD000– FFFFEFFF — 8 MCSCR0 BSC I FFFFFF50 16
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Control Register RWKAR 1 2 Module* Bus* RTC P 4 Address* FFFFFED6 3 Size (Bits) Access Size (Bits)* 8 8 RDAYAR RTC P FFFFFED8 8 8 RMONAR RTC P FFFFFEDA 8 8 RCR1 RTC P FFFFFEDC 8 8 RCR2 RTC P FFFFFEDE 8 8 ICR0 INTC I FFFFFEE0 16 16 IPRA INTC I FFFFFEE2 16 16 IPRB INTC I FFFFFEE4 16 16 TOCR TMU P FFFFFE90 8 8 TSTR TMU P FFFFFE92 8 8 TCOR0 TMU P FFFFFE94 32 32 TCNT0 TMU P FFFFFE98 32 32 TCR0 TMU P FFFFFE9C 16 16 TCOR1 TMU P
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1 2 4 Address* 3 Module* Bus* ICR1 INTC I 4000010 16 16 ICR2 INTC I 4000012 16 16 PINTER INTC I 4000014 16 16 IPRC INTC I 4000016 16 16 IPRD INTC I 4000018 16 16 IPRE INTC I 400001A 16 16 SAR0 DMAC P 4000020 32 16,32 DAR0 DMAC P 4000024 32 16,32 DMATCR0 DMAC P 4000028 32 16,32 CHCR0 DMAC P 400002C 32 8,16,32 SAR1 DMAC P 4000030 32 16,32 DAR1 DMAC P 4000034 32 16,32 DMATCR1 DMAC P 4000038 32 16,32 CHCR1 DMAC P 400003C 32
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1 2 4 Address* 3 Module* Bus* ADDRCL A/D P 400008A 8 ADDRDH A/D P 400008C 8 ADDRDL A/D P 400008E 8 5 6 8,16,32* * 5 8,16* ADCSR A/D P 4000090 8 5 6 8,16,32* * ADCR A/D P 4000092 8 8,16 DADR0 D/A P 40000A0 8 DADR1 D/A P 40000A2 8 5 6 8,16,32* * 5 8,16* DACR D/A P 40000A4 8 8,16,32 PACR PORT P 4000100 16 16 PBCR PORT P 4000102 16 16 PCCR PORT P 4000104 16 16 PDCR PORT P 4000106 16 16 PECR PORT P 4000108 16 16 PFCR PORT P 4000
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1 2 Module* Bus* SCSMR1 IrDA P SCBRR1 IrDA SCSCR1 IrDA SCFTDR1 4 Address* 3 Size (Bits) Access Size (Bits)* 4000140 8 8 P 4000142 8 8 P 4000144 8 8 IrDA P 4000146 8 8 SCSSR1 IrDA P 4000148 16 16 SCFRDR1 IrDA P 400014A 8 8 SCFCR1 IrDA P 400014C 8 8 Control Register SCFDR1 IrDA P 400014E 16 16 SCSMR2 SCIF P 4000150 8 8 SCBRR2 SCIF P 4000152 8 8 SCSCR2 SCIF P 4000154 8 8 SCFTDR2 SCIF P 4000156 8 8 SCSSR2 SCIF P 4000158 16 16
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B.2 Register Bits Table B.
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Register TCR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module — — — — — — — UNF TMU — — UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TCOR2 TMU TCNT2 TMU TCR2 — — — — — — ICPF UNF ICPE1 ICPE0 UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TCPR2 TMU TMU R64CNT — 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz RTC RSECCNT — 10 sec 1 sec RTC RMINCNT — 10 min 1 min RTC RHRCNT — — 1 hour RTC RWKCNT — — RDAYCNT — — RMONCNT — — RYRCNT 10 hours — — — 10
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Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module CF — — CIE AIE — — AF RTC RCR2 PEF PES2 PES1 PES0 RTCEN ADJ RESET START RTC ICR0 NML — — — — — — NMIE INTC — — — — — — — — RCR1 IPRA IPRB TMU0 TMU1 TMU2 RTC WDT REF SCI BCR1 PULA PULD — — INTC INTC — A5BST0 A6BST1 A6BST0 DRAMTP2 DRAMTP1 DRAMTP0 A5PCM BCR2 WCR1 WCR2 MCR PCR — HIZMEM HIZCNT ENDIAN A0BST1 A0BST0 A5BST1 BSC A6PCM — — A6SZ1 A6SZ0 A5SZ1 A5SZ0 A4SZ1 A4SZ0
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Register RFCR FRQCR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module — — — — — — — — BSC STC2 IFC2 PFC2 — — — SLPFRQ CKOEN CPG IFC0 PFC1 PLLEN PSTBY STC1 STC0 IFC1 STBCR STBY — — STBXTL — STBCR2 MSTP9 MDCHG MSTP8 MSTP7 PFC0 MSTP2 MSTP1 MSTP0 MSTP6 MSTP5 MSTP4 MSTP3 WTCNT WTCSR CPG CPG CPG TME WT/IT RSTS WOVF IOVF CKS2 CKS1 CKS0 CPG BDRB UBC BDMRB UBC BRCR — — — — — — — — — — BASMA BASMB — — — — SCMFCA SCMFCB PCTE PC
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Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BAMRA BBRA BETR BRSR BRDR TRA EXPEVT INTEVT MMUCR Module UBC — — — — — — — — CDA1 CDA0 IDA1 IDA0 RWA1 RWA0 SZA1 SZA0 — — — — UBC UBC SVF PID2 PID1 PID0 BSA27 BSA26 BSA25 BSA24 BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16 BSA15 BSA14 BSA13 BSA12 BSA11 BSA10 BSA9 BSA8 BSA7 BSA6 BSA5 BSA4 BSA3 BSA2 BSA1 BSA0 DVF — — — BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BD
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Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BASRA UBC BASRB CCR Module UBC — — — — — — — — — — — — — — — — — — — — — — — — — — 0 0 CF CB WT CE CDR2 CCN CCN W3LOAD W3LOCK W2LOAD W2LOCK PTEH CCN — — PTEL CCN — PR PR SZ C D — V SH — TTB CCN TEA CCN INTEVT2 INTC Rev. 5.
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Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRR0 INTC PINT0R PINT1R IRQ5R IRQ4R IRQ3R IRQ2R IRQ1R IRQ0R IRR1 INTC TXI1R BRI1R RXI1R ERI1R DEI3R DEI2R DEI1R DEI0R IRR2 ICR1 ICR2 PINTER Module INTC — — — ADIR TXI2R BRI2R RXI2R ERI2R MAI IRQLVL BLMSK — IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S PINT15S PINT14S PINT13S PINT12S PINT11S PINT10S PINT9S PINT8S PINT7S PINT1S PINT0S PINT15E PINT14E PINT1
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Register CHCR0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module — — — — — — — — DMAC — — — — — RL AM AL DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 — DS TM TS1 TS0 IE TE DE SAR1 DMAC DAR1 DMAC DMATCR1 — — — — — — — — DMAC CHCR1 — — — — — — — — DMAC — — — — — RL AM AL DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 — DS TM TS1 TS0 IE TE DE SAR2 DMAC DAR2 DMAC DMATCR2 — — — Rev. 5.
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Register CHCR2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module — — — — — — — — DMAC — — — — RO — — — DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 — — TM TS1 TS0 IE TE DE SAR3 DMAC DAR3 DMAC DMATCR3 — — — — — — — — DMAC CHCR3 — — — — — — — — DMAC — — — DI — — — — DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 — — TM TS1 TS0 IE TE DE — — — — — — PR1 PR0 — — — — — AE NMIF DME CMSTR — — — — — — — — — — — — — — —
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Register ADDRBH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/DC ADDRBL AD1 AD0 — — — — — — A/DC ADDRCH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/DC ADDRCL AD1 AD0 — — — — — — A/DC ADDRDH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/DC ADDRDL AD1 AD0 — — — — — — A/DC ADCSR ADF ADE ADST MULT1 CKS CH2 CH1 CH0 A/DC TRGE1 TRGE2 SCN — — — A/DC ADCR RESVD1 RESVD2 DADR0 D/AC DADR1 D/AC DACR DAOE1 D
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Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PG7M D1 PG7M D0 PG6M D1 PG6M D0 PG5M D1 PG5M D0 PG4M D1 PG4M D0 PORT PG3M D1 PG3M D0 PG2M D1 PG2M D0 PG1M D1 PG1M D0 PG0M D1 PG0M D0 PH7M D1 PH7M D0 PH6M D1 PH6M D0 PH5M D1 PH5M D0 PH4M D1 PH4M D0 PH3M D1 PH3M D0 PH2M D1 PH2M D0 PH1M D1 PH1M D0 PH0M D1 PH0M D0 PJ7M D1 PJ7M D0 PJ6M D1 PJ6M D0 PJ5M D1 PJ5M D0 PJ4M D1 PJ4M D0 PJ3M D1 PJ3M D0 PJ2M D1 PJ2M D0 PJ1M D1 PJ1M D0 PJ0M D1 PJ0M D0
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Register SDIR SCSMR1 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Module TI3 TI2 TI1 TI0 — — — — UDI — — — — — — — — IRM0D ICK3 ICK2 ICK1 ICK0 PSEL CKS1 CKS0 SCBRR1 SCSCR1 IrDA TIE RIE TE RE — — CKE1 CKE0 SCFTDR1 SCSSR1 IrDA IrDA IrDA PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 ER TEND TDFE BRK FER PER RDF DR SCFRDR1 IrDA IrDA SCFCR1 RTRG1 RTRG0 TTRG1 TTRG0 MCE TFRST RFRST LOOP IrDA SCFDR1 — — — T4 T3 T2 T1 T0 IrDA — — — R4 R3
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Appendix C Product Lineup Table C.1 SH7709S Models Power Supply Voltage I/O Internal Operating Frequency 3.3±0.3 V 2.0±0.15 V 200 MHz HD6417709SHF200B 208-pin plastic HQFP (FP-208E) 1.9±0.15 V 167 MHz HD6417709SF167B 208-pin plastic LQFP (FP-208C) HD6417709SBP167B 240-pin CSP (BP-240A) HD6417709SF133B 208-pin plastic LQFP (FP-208C) HD6417709SBP133B 240-pin CSP (BP-240A) HD6417709SF100B 208-pin plastic LQFP (FP-208C) HD6417709SBP100B 240-pin CSP (BP-240A) Abbr. SH7709S 1.8+0.25 V 1.
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Appendix D Package Dimensions Figures D.1 to D.3 show the SH7709S package dimensions. Unit: mm 30.0 ± 0.2 28 105 156 104 208 53 0.5 30.0 ± 0.2 157 52 *Dimension including the plating thickness Base material dimension 1.25 0.5 ± 0.1 Package Code JEDEC JEITA Mass (reference value) Figure D.1 Package Dimensions (FP-208C) Rev. 5.00, 09/03, page 758 of 760 1.0 0° − 8° 0.10 ± 0.05 0.08 *0.17 ± 0.05 0.15 ± 0.04 0.08 M 1.40 0.20 ± 0.04 1.70 Max 1 *0.22 ± 0.05 FP-208C − Conforms 2.
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30.6 ± 0.2 Unit: mm 28 105 156 104 208 53 0.10 *Dimension including the plating thickness Base material dimension *0.17 ± 0.05 0.15 ± 0.04 52 0.10 M 3.20 0.20 ± 0.04 0.15 +0.10 −0.15 1 *0.22 ± 0.05 3.56 Max 0.5 30.6 ± 0.2 157 1.3 1.25 0° − 8° 0.5 ± 0.1 Package Code JEDEC JEITA Mass (reference value) FP-208E − Conforms 5.3 g Figure D.2 Package Dimensions (FP-208E) Rev. 5.
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13.00 0.20 C A 0.65 0.20 C B Unit: mm 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 A B C D E F G H J K L M N P R T U V W 0.65 13.00 B A 4× 0.15 0.65 240 × φ0.40 ± 0.05 φ0.08 M C A B 0.2 C 0.33 ± 0.05 C 1.40Max 0.10 C Package Code JEDEC JEITA Mass (reference value) Figure D.3 Package Dimensions (BP-240A) Rev. 5.00, 09/03, page 760 of 760 0.65 BP-240A − − 0.
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SH7709S Group Hardware Manual Publication Date: 1st Edition, September 2001 Rev.5.00, September 18, 2003 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. ©2001, 2003 Renesas Technology Corp. All rights reserved. Printed in Japan.
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Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str.
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SH7709S Group Hardware Manual REJ09B0081-0500O (ADE-602-250C)