APPLICATION NOTE SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) Introduction This application note describes the operation of the DMAC, and is intended for reference to help in the design of user software. Target Device SH7211 Contents 1. Introduction ....................................................................................................................................... 2 2. Description of Sample Application .........................................
SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) 1. 1.1 Introduction Specification • DMAC channel 0 is used. • Auto-request mode is used as the interrupt source for activating DMA transfer. • Cycle-stealing mode is used as the bus mode. 1.2 Used Module • Direct memory access controller (DMAC channel 0) 1.
SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) 2. Description of Sample Application In this sample application, the direct memory access controller (DMAC) is set to auto request mode to transfer 512Kbtyte data stored in the on-chip RAM to another address. 2.
SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) In the normal mode of cycle stealing, bus mastership is given to another bus master after each DMA transfer of one transfer unit (byte, word, longword, or 16-byte unit). When a subsequent transfer request occurs, bus mastership is obtained from the other bus master and transfer proceeds for one transfer unit. When that transfer ends, the bus mastership is passed to another bus master.
SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) DMAC module RDMATCR_n On-chip memory Iteration control RSAR_n Register control Internal bus Peripheral bus On-chip peripheral module DMATCR_n SAR_n RDAR_n Start-up control DAR_n DMA transfer request signal CHCR_n DMA transfer acknowledge signal HEIn Interrupt controller DEIn Request priority control DMAOR DMARS0 to DMARS3 External ROM Bus interface External RAM External device (memory mapped) External dev
SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) 2.2 Operational Description of Sample Program The settings of the DMAC for the sample program are listed in table 4. Also, the operation of the sample program is illustrated in figure 4.
SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) 2.3 Procedure for Setting Modules This section describes the procedure for making initial settings when the DMAC is to be used to transfer data between locations within the on-chip RAM. Auto request mode is used for the transfer requests. By default, the on-chip peripheral modules of this MCU are in module standby mode.
SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) DMAC_init Set DMA channel control register (CHCR_0) [1] [2] Set the DMA transfer source address (SAR_0) Specify the DMA transfer source address Set DMA source address register (SAR_0) [2] Set DMA destination address register (DAR_0) [3] Set DMA transfer count register (DMATCR_0) [4] Set DMA channel control register (CHCR_0) [5] Set DMA operation register (DMAOR) [6] END [1] Disable DMA transfer Set the DE (DM
SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) 2.4 2.4.1 Register Settings for Sample Program Clock Pulse Generator (CPG) The settings of the clock pulse generator for the sample program are described in table 5. Table 5 Settings of Clock Pulse Generator Register Name Frequency control register (FRQCR) 2.4.
SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) 2.4.3 Direct Memory Access Controller (DMAC) The settings of DMAC registers for the sample program are described in table 7.
SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) 3. Documents for Reference • Software Manual SH-2A, SH2A-FPU Software Manual The most up-to-date version of this document is available on the Renesas Technology Website. • Hardware Manual SH7211 Group Hardware Manual The most up-to-date version of this document is available on the Renesas Technology Website. REJ06B0732-0100/Rev.1.
SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) Website and Support Renesas Technology Website http://www.renesas.com/ Inquiries http://www.renesas.com/inquiry csc@renesas.com Revision Record Rev. 1.00 Date Mar.21.08 Description Page Summary — First edition issued All trademarks and registered trademarks are the property of their respective owners. REJ06B0732-0100/Rev.1.
SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) Notes regarding these materials 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use.
