Hardware manual

R8C/10 Group
Rev.1.20 Jan 27, 2006 page 38 of 180
REJ09B0019-0120
10.1.5 Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in
which order they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the FLG register’s I flag, IPL, and each interrupt control register's ILVL2 to ILVL0 bits to enable/
disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each
interrupt control register.
Figure 10.3 shows the interrupt control registers.
10.1 Interrupt Overview