REJ09B0019-0120 R8C/10 Group 16 Hardware Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / R8C /Tiny SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.
Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
How to Use This Manual 1. Introduction This hardware manual provides detailed information on the R8C/10 Group of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit function in each register are shown below.
3. M16C Family Documents The following documents were prepared for the M16C family. (1) Document Contents Short Sheet Hardware overview Data Sheet Hardware overview and electrical characteristics Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, timing charts). *Refer to the application note for how to use peripheral functions.
Table of Contents SFR Page Reference Chapter 1. Overview ............................................................. 1 1.1 1.2 1.3 1.4 1.5 1.6 Applications ................................................................................................................... 1 Performance Overview .................................................................................................. 2 Block Diagram ...................................................................................................
.3 CPU Clock and Peripheral Function Clock ................................................................ 23 6.3.1 CPU Clock .............................................................................................................................................. 23 6.3.2 Peripheral Function Clock (f1, f2, f8, f32, fAD, f1SIO, f8SIO, f32SIO) ....................................................... 23 6.3.3 fRING and fRING128 .............................................................................
12.3.3 Programmable One-shot Generation Mode ...................................................................................... 80 12.3.4 Programmable Wait One-shot Generation Mode ............................................................................. 83 12.4 Timer C ........................................................................................................................ 86 Chapter 13. Serial Interface ................................................ 89 13.
Chapter 18. On-chip Debugger ........................................ 161 18.1 Address Match Interrupt .......................................................................................... 161 18.2 Single Step Interrupt ................................................................................................ 161 18.3 UART1 ........................................................................................................................ 161 18.4 BRK Instrucstion ............................
SFR Page Reference Address Register Symbol Page 000016 Address 004016 000116 004116 000216 004216 000516 000616 000716 PM0 PM1 CM0 CM1 31 31 19 19 004416 Address match interrupt enable register AIER Protect register PRCR 52 30 004916 Oscillation stop detection register Watchdog timer reset register Watchdog timer start register Watchdog timer control register Address match interrupt register 0 20 54 54 54 52 004C16 Processor mode register 0 Processor mode register 1 System clock control
SFR Page Reference Address 008016 008116 008216 008316 008416 008516 008616 008716 Symbol Page TYZMR 65/73 PREY 66 TYSC 66 TYPR 66 Timer Y, Z waveform output control register PUM 67/75 Prescaler Z register PREZ 74 Timer Z secondary register TZSC 74 Timer Z primary register TZPR 74 Register Timer Y, Z mode register Prescaler Y register Timer Y secondary register Timer Y primary register 00C016 008C16 008D16 008E16 00C316 00C416 00C516 00C616 00C716 00C816 00C916 Timer Y, Z output control register Timer
R8C/10 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER REJ09B0019-0120 Rev.1.20 Jan 27, 2006 1. Overview This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing instructions at high speed. 1.
R8C/10 Group 1. Overview 1.2 Performance Overview Table 1.1. lists the performance outline of this MCU. Table 1.1 Performance outline Item Performance CPU Number of basic instructions 89 instructions Minimum instruction execution time 62.5 ns (f(XIN) = 16 MHZ, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHZ, VCC = 2.7 to 5.5 V) Operating mode Single-chip Address space 1M bytes Memory capacity See Table 1.
R8C/10 Group 1. Overview 1.3 Block Diagram Figure 1.1 shows this MCU block diagram.
R8C/10 Group 1. Overview 1.4 Product Information Table 1.2 lists the product inforamation. Table 1.2 Product Information As of January 2006 ROM capacity RAM capacity R5F21102FP 8K bytes 512 bytes PLQP0032GB-A R5F21103FP 12K bytes 768 bytes PLQP0032GB-A R5F21104FP 16K bytes 1K bytes PLQP0032GB-A R5F21102DFP 8K bytes 512 bytes PLQP0032GB-A R5F21103DFP 12K bytes 768 bytes PLQP0032GB-A R5F21104DFP 16K bytes 1K bytes PLQP0032GB-A Type No. Type No.
R8C/10 Group 1. Overview 1.5 Pin Assignment Figure 1.3 shows the pin Assignments (top view).
R8C/10 Group 1. Overview 1.6 Pin Description Table 1.3 shows the pin description Table 1.3 Pin description Signal name Power supply input IVcc Pin name Vcc, Vss IVcc Analog power supply input AVcc, AVss Reset input CNVss MODE Main clock input RESET CNVss MODE XIN I/O type I O I Power supply input pins for A/D converter. Connect the AVcc pin to Vcc. Connect the AVss pin to Vss. Connect a capacitor between pins AVcc and AVss. I I I I Input “L” on this pin resets the MCU.
R8C/10 Group 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. Two sets of register banks are provided.
R8C/10 Group 2. Central Processing Unit (CPU) 2.2 Address Registers (A0 and A1) A0 is a 16-bit register for address register indirect addressing and address register relative addressing. They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0 can be combined with A0 to be used as a 32-bit address register (A1A0). 2.3 Frame Base Register (FB) FB is a 16-bit register for FB relative addressing. 2.
R8C/10 Group 3. Memory 3. Memory Figure 3.1 is a memory map of this MCU. This MCU provides 1-Mbyte address space from addresses 0000016 to FFFFF16. The internal ROM is allocated lower addresses beginning with address 0FFFF16. For example, a 16Kbyte internal ROM is allocated addresses from 0C00016 to 0FFFF16. The fixed interrupt vector table is allocated addresses 0FFDC16 to 0FFFF16. They store the starting address of each interrupt routine.
R8C/10 Group 4. Special Function Register (SFR) 4. Special Function Register (SFR) SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR information Table 4.
R8C/10 Group 4. Special Function Register (SFR) Table 4.
R8C/10 Group 4. Special Function Register (SFR) Table 4.
R8C/10 Group 4. Special Function Register (SFR) Table 4.
R8C/10 Group 5. Reset 5. Reset There are three types of resets: a hardware reset, a software reset, and an watchdog timer reset. 5.1 Hardware Reset ____________ ____________ A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the power supply voltage is within the recommended operating condition, the pins are initial____________ ized (see Table 5.1 “Pin Status When RESET Pin Level is 'L'”).
R8C/10 Group 5.
R8C/10 Group 5. Reset 2.7V VCC 0V RESET VCC RESET Equal to or less than 0.2VCC 0V More than td(P-R) + 500 µs are needed. Figure 5.3 Example Reset Circuit 5V 2.7V VCC RESET VCC Supply voltage detection circuit 0V 5V RESET 0V More than td(P-R) + 500 µs are needed. Example when VCC = 5V. Figure 5.4 Example Reset Circuit (Voltage Check Circuit) Rev.1.
R8C/10 Group 6. Clock Generation Circuit 6. Clock Generation Circuit The clock generation circuit contains two oscillator circuits as follows: • Main clock oscillation circuit • On-chip oscillator (with oscillation stop detection function) Table 6.1 lists the clock generation circuit specifications. Figure 6.1 shows the clock generation circuit. Figures 6.2 and 6.3 show the clock-related registers. Table 6.
R8C/10 Group 6.
6.
R8C/10 Group 6.
R8C/10 Group 6.1 Main Clock The following describes the clocks generated by the clock generation circuit. 6.1 Main Clock This clock is supplied by a main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a resonator between the XIN and XOUT pins.
R8C/10 Group 6.2 On-chip Oscillator Clock 6.2 On-Chip Oscillator Clock This clock, approximately 125 kHz, is supplied by the on-chip oscillator. This clock is used as the clock source for the CPU clock, peripheral function clock, fRING, and fRING128. After reset, the on-chip oscillator clock divided by 8 is selected for the CPU clock. To use the main clock for the CPU clock, set the OCD2 in the OCD register to “0” (selecting main clock) after the main clock becomes oscillating stably.
R8C/10 Group 6.3 CPU Clock and Peripheral Function Clock 6.3 CPU Clock and Peripheral Function Clock There are two types of clocks: CPU clock to operate the CPU and peripheral function clock to operate the peripheral functions. Also refer to “Figure 6.1 Clock Generating Circuit”. 6.3.1 CPU Clock This is an operating clock for the CPU and watchdog timer. The clock source for the CPU clock can be chosen to be the main clock or on-chip oscillator clock.
R8C/10 Group 6.4 Power Control 6.4 Power Control There are three power control modes. All modes other than wait and stop modes are referred to as normal operation mode. 6.4.1 Normal Operation Mode Normal operation mode is further classified into three modes. In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock frequency.
6.4 Power Control R8C/10 Group 6.4.2 Wait Mode In wait mode, the CPU clock is turned off, so are the CPU and the watchdog timer because both are operated by the CPU clock. Because the main clock and on-chip oscillator clock both are on, the peripheral functions using these clocks keep operating.
R8C/10 Group 6.4 Power Control 6.4.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of power is consumed in this mode. If the voltage applied to Vcc pin is VRAM or more, the internal RAM is retained. However, the peripheral functions clocked by external signals keep operating.
R8C/10 Group 6.4 Power Control Figure 6.5 shows the state transition of Power control Reset There are five power control modes.
6.5 Oscillation Stop Detection Function R8C/10 Group 6.5 Oscillation Stop Detection Function The oscillation stop detection function is such that main clock oscillation circuit stop is detected. The oscillation stop detection function can be enabled and disabled by the OCD1 to OCD0 bits in the OCD register. Table 6.4 lists the specifications of the oscillation stop detection function.
R8C/10 Group 6.5 Oscillation Stop Detection Function Table 6.
R8C/10 Group 7. Protection 7. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 7.1 shows the PRCR register. The following lists the registers protected by the PRCR register.
R8C/10 Group 8. Processor Mode 8. Processor Mode 8.1 Types of Processor Mode The processor mode is single-chip mode. Table 8.1 shows the features of the processor mode. Figure 8.1 shows the PM0 and PM1 register. Table 8.
R8C/10 Group 9. Bus 9. Bus During access, the ROM/RAM and the SFR have different bus cycles. Table 9.1 shows bus cycles for access space. The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word (16 bits) units, these spaces are accessed twice in 8-bit units. Table 9.2 shows bus cycles in each access space. Table 9.1 Bus Cycles for Access Space Access space Bus cycle SFR/Data flash 2 CPU clock cycles Program ROM/RAM 1 CPU clock cycles Table 9.
R8C/10 Group 10.1 Interrupt Overview 10. Interrupt 10.1 Interrupt Overview 10.1.1 Type of Interrupts Figure 10.1 shows types of interrupts. Hardware Interrupt Software (Non-maskable interrupt) Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Watchdog timer Oscillation stop detection Special Single step(2) (Non-maskable interrupt) Address match Peripheral function(1) (Maskable interrupt) NOTES: 1.
10.1 Interrupt Overview R8C/10 Group 10.1.2 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are nonmaskable interrupts. • Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. • Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the operation resulted in an overflow).
10.1 Interrupt Overview R8C/10 Group 10.1.3 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. (1) Special Interrupts Special interrupts are non-maskable interrupts. • Watchdog Timer Interrupt Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize the watchdog timer. For details about the watchdog timer, refer to Chapter 11, “Watchdog Timer.
R8C/10 Group 10.1 Interrupt Overview 10.1.4 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector. Figure 10.2 shows the interrupt vector.
R8C/10 Group 10.1 Interrupt Overview • Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a relocatable vector table area. Table 10.2 lists interrupts and vector tables located in the relocatable vector table. Table 10.
R8C/10 Group 10.1 Interrupt Overview 10.1.5 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use the FLG register’s I flag, IPL, and each interrupt control register's ILVL2 to ILVL0 bits to enable/ disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control register. Figure 10.
R8C/10 Group 10.
R8C/10 Group 10.1 Interrupt Overview • I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts. • IR Bit The IR bit is set to “1” (interrupt requested) when an interrupt request is generated. Then, when the interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is cleared to “0” (= interrupt not requested).
R8C/10 Group 10.1 Interrupt Overview • Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle.
R8C/10 Group 10.1 Interrupt Overview • Interrupt Response Time Figure 10.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when the instruction then executing is completed (see #a in Figure 10.
10.1 Interrupt Overview R8C/10 Group • Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits in the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits in the PC are saved. Figure 10.6 shows the stack status before and after an interrupt request is accepted.
R8C/10 Group 10.1 Interrupt Overview • Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Thereafter the CPU returns to the program which was being executed before accepting the interrupt request.
R8C/10 Group 10.1 Interrupt Overview • Interrupt Priority Resolution Circuit The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those requested. Figure 10.9 shows the Interrupts Priority Select Circuit.
R8C/10 Group 10.2 INT Interrupt ______ 10.2 INT Interrupt ________ 10.2.1 INT0 Interrupt _______ INT0 interrupt is triggered by an INT0 input. When using INT0 interrupts, the INT0EN bit in the INTEN register must be set to “1” (enabling). The edge polarity is selected using the INT0PL bit in the INTEN register and the POL bit in the INT0IC register. Inputs can be passed through a digital filter with three different sampling clocks.
R8C/10 Group 10.2 INT Interrupt _______ 10.2.2 INT0 Input Filter _______ The INT0 input has a digital filter which can be sampled by one of three sampling clocks. The sampling clock is selected using the INT0F1 to INT0F0 bits in the INT0F register. The IR bit in the INT0IC register is set to “1” (interrupt requested) when the sampled input level matches three times. When the INT0F1 to INT0F0 bits are set to “012”, “102”, or “112”, the P4_5 bit in the P4 register indicates the filtered value.
R8C/10 Group 10.2 INT Interrupt ______ ______ 10.2.3 INT1 Interrupt and INT2 Interrupt ______ ______ INT1 interrupts are triggered by INT1 inputs. The edge polarity is selected with the R0EDG bit in the ______ TXMR register. The INT1 pin is shared with the CNTR0 pin. ______ ______ INT2 interrupts are triggered by INT2 inputs. The edge polarity is selected with the R1EDG bit in the ______ TYZMR register. The INT2 pin is shared with the CNTR1 pin. ______ _____ Figure 10.
R8C/10 Group 10.2 INT Interrupt ______ 10.2.4 INT3 Interrupt _____ ______ INT3 interrupts are triggered by INT3 inputs. The TCC07 bit in the TCC0 register should be se to “0” ______ _______ (INT3). The INT3 input has a digital filter which can be sampled by one of three sampling clocks. The sampling clock is selected using the TCC11 to TCC10 bits in the TCC1 register. The IR bit in the INT3IC register is set to “1” (interrupt requested) when the sampled input level matches three times.
R8C/10 Group 10.3 Key Input Interrupt 10.3 Key Input Interrupt _____ _____ A key input interrupt is generated on an input edge of any of the K10 to K13 pins. Key input interrupts can _____ be used as a key-on wakeup function to exit wait or stop mode. KIi input can be enabled or disabled selecting with the KIiEN (i=0 to 3) bit in the KIEN register. The edge polarity can be rising edge or falling _____ edge selecting with the KIiPL bit in the KIEN register.
R8C/10 Group 10.4 Address Match Interrupt 10.4 Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMADi register (i=0, 1). Set the start address of any instruction in the RMADi register. Use the AIER0 and AIER1 bits in the AIER register to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL.
R8C/10 Group 10.4 Address Match Interrupt Address match interrupt enable register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Address 000916 After reset XXXXXX002 AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA Bit symbol Function RW AIER0 Address match interrupt 0 enable bit Bit name 0 : Interrupt disabled 1 : Interrupt enabled RW AIER1 Address match interrupt 1 enable bit 0 : Interrupt disabled 1 : Interrupt enabled RW (b7-b2) Nothing is assigned. When write, set to “0”.
R8C/10 Group 11. Watchdog Timer 11. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the CPU clock using the prescaler.
R8C/10 Group 11.
R8C/10 Group 12. Timers 12. Timers The microcomputer has three 8-bit timers and one 16-bit timer. The three 8-bit timers are Timer X, Timer Y, and Timer Z and each one has an 8-bit prescaler. The 16-bit timer is Timer C and has a capture. All these timers function independently. The count source for each timer is the operating clock that regulates the timing of timer operations such as counting and reloading. Table 12.1 lists functional comparison. Table 12.
12.1 Timer (Timer X) R8C/10 Group 12.1 Timer X The Timer X is an 8-bit timer with an 8-bit prescaler. Figure 12.1 shows the block diagram of Timer X. Figures 12.2 and 12.3 show the Timer X-related registers. The Timer X has five operation modes listed as follows: • Timer mode: The timer counts an internal count source. • Pulse output mode: The timer counts an internal count source and outputs the pulses whose polarity is inverted at the timer the timer underflows.
R8C/10 Group 12.
12.1 Timer (Timer X) R8C/10 Group 12.1.1 Timer Mode In this mode, the timer counts an internally generated count source (See “Table 12.2 Timer Mode Specifications”). Figure 12.4 shows the TXMR register in timer mode. Table 12.
R8C/10 Group 12.1 Timer (Timer X) 12.1.2 Pulse Output Mode In this mode, the timer counts an internally generated count source, and outputs from the CNTR0 pin a pulse whose polarity is inverted each time the timer underflows (See “Table 12.3 Pulse Output mode Specifications”). Figure 12.5 shows TXMR register in pulse output mode. Table 12.
12.1 Timer (Timer X) R8C/10 Group 12.1.3 Event Counter Mode _____ In this mode, the timer counts an external signal fed to INT1/CNTR0 pin (See “Table 12.4 Event Counter Mode Specifications”). Figure 12.6 shows TXMR register in event counter mode. Table 12.
12.1 Timer (Timer X) R8C/10 Group 12.1.4 Pulse Width Measurement Mode _____ In this mode, the timer measures the pulse width of an external signal fed to INT1/CNTR0 pin (See “Table 12.5 Pulse Width Measurement Mode Specifications”). Figure 12.7 shows the TXMR register in pulse width measurement mode. Figure 12.8 shows an operation example in pulse width measurement mode. Table 12.
R8C/10 Group 12.
R8C/10 Group 12.1 Timer (Timer X) 12.1.5 Pulse Period Measurement Mode In this mode, the timer measures the pulse period of an external signal fed to INT1/CNTR0 pin (See “Table 12.6 Pulse Period Measurement Mode Specifications”). Figure 12.9 shows the TXMR register in pulse period measurement mode. Figure 12.10 shows an operation example in pulse period measurement mode. Table 12.
R8C/10 Group 12.
R8C/10 Group 12.2 Timer (Timer Y) 12.2 Timer Y Timer Y is an 8-bit timer with an 8-bit prescaler and has two reload registers-Timer Y Primary and Timer Y Secondary. Figure 12.11 shows a block diagram of Timer Y. Figures 12.12 to 12.14 show the TYZMR, PREY, TYSC, TYPR, TYZOC, PUM, and YCSS registers. The Timer Y has two operation modes as follows: • Timer mode: The timer counts an internal count source. • Programmable waveform generation mode: The timer outputs pulses of a given width successively.
R8C/10 Group 12.
R8C/10 Group 12.
R8C/10 Group 12.2 Timer (Timer Y) 12.2.1 Timer Mode In this mode, the timer counts an internally generated count source (see “Table 12.7 Timer Mode Specifications”). An external signal input to the CNTR1 pin can be counted. The TYSC register is unused in timer mode. Figure 12.15 shows the TYZMR and PUM registers in timer mode. Table 12.
R8C/10 Group 12.
R8C/10 Group 12.2 Timer (Timer Y) 12.2.2 Programmable Waveform Generation Mode In this mode, an signal output from the TYOUT pin is inverted each time the counter underflows, while the values in the TYPR register and TYSC register are counted alternately (see “Table 12.8 Programmable Waveform Generation Mode Specifications”). A counting starts by counting the set value in the TYPR register. Figure 12.16 shows the TYZMR register in programmable waveform generation mode. Figure 12.
R8C/10 Group 12.
R8C/10 Group 12.
R8C/10 Group 12.3 Timer (Timer Z) 12.3 Timer Z Timer Z is an 8-bit timer with an 8-bit prescaler and has two reload registers-Timer Z Primary and Timer Z Secondary. Figure 12.18 shows a block diagram of Timer Z. Figures 12.19 to 12.21 show the TYZMR, PREZ, TZSC, TZPR, TYZOC, PUM, and TCSS registers. Timer Z has the following four operation modes. • Timer mode: The timer counts an internal count source or Timer Y underflow.
R8C/10 Group 12.
R8C/10 Group 12.
R8C/10 Group 12.3 Timer (Timer Z) 12.3.1 Timer Mode In this mode, the timer counts an internally generated count source or Timer Y underflow (see “Table 12.9 Timer Mode Specifications”). The Timer Z secondary is unused in timer mode. Figure 12.22 shows the TYZMR register and PUM register in timer mode. Table 12.
R8C/10 Group 12.
12.3 Timer (Timer Z) R8C/10 Group 12.3.2 Programmable Waveform Generation Mode In this mode, an signal output from the TZOUT pin is inverted each time the counter underflows, while the values in the TZPR register and TZSC register are counted alternately (see “Table 12.10 Programmable Waveform Generation Mode Specifications”). A counting starts by counting the value set in the TZPR register. Figure 12.23 shows TYZMR and PUM registers in this mode.
R8C/10 Group 12.
R8C/10 Group 12.3 Timer (Timer Z) 12.3.3 Programmable One-shot Generation Mode In this mode, upon program command or external trigger input (input to the INT0 pin), the microcomputer outputs the one-shot pulse from the TZOUT pin (see “Table 12.11 Programmable One-shot Generation Mode Specifications”). When a trigger occurs, the timer starts operating from the point only once for a given period equal to the set value in the TZPR register. The TZSC is unused in this mode. Figure 12.
R8C/10 Group 12.3 Timer (Timer Z) Timer Y, Z mode register b7 b6 b5 b4 b3 b2 b1 b0 1 1 0 Symbol TYZMR Address 008016 Bit symbol Bit name TYMOD0 Timer Y-related bit After reset 0016 Function RW RW R1EDG RW TYWC RW TYS RW b5 b4 TZMOD0 Timer Z operation mode bit 1 0 : Programmable one-shot generation mode TZMOD1 TZWC RW RW Timer Z write control bit Set to "1" in programmable one-shot generation mode(1) Timer Z count 0 : Stops counting TZS start flag 1 : Starts counting NOTES: 1.
R8C/10 Group 12.
R8C/10 Group 12.3 Timer (Timer Z) 12.3.4 Programmable Wait One-shot Generation Mode In this mode, upon program or external trigger input (input to the INT0 pin), the microcomputer outputs the one-shot pulse from the TZOUT pin after waiting for a given length of time (see “Table 12.12 Programmable Wait One-shot Generation Mode Specifications”).
R8C/10 Group 12.
R8C/10 Group 12.
R8C/10 Group 12.4 Timer (Timer C) 12.4 Timer C Timer C is a 16-bit free-running timer. Figure 12.28 shows a block diagram of Timer C. The Timer C uses an edge input to TCIN pin or the fRING128 clock as trigger to latch the timer count value and generates an interrupt request. The TCIN input has a digital filter and this prevents an error caused by noise or so on from occurring. Table 12.13 shows Timer C specifications. Figure 12.29 shows TC, TM0, TCC0, and TCC1 registers. Figure 12.
R8C/10 Group 12.
12.
R8C/10 Group 13. Serial Interface 13. Serial Interface Serial interface is configured with two channels: UART0 to UART1. UART0 and UART1 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 13.1 shows a block diagram of UARTi (i=0, 1). Figure 13.2 shows a block diagram of the UARTi transmit/receive. UART0 has two modes: clock synchronous serial I/O mode, and clock asynchronous serial I/O mode (UART mode).
R8C/10 Group 13.
R8C/10 Group 13. Serial Interface UARTi transmit buffer register(1, 2) (i=0, 1) (b15) b7 (b8) b0 b7 b0 Symbol U0TB U1TB Address 00A316-00A216 00AB16-00AA16 Bit symbol (b8-b0) (b15-b9) After reset Indeterminate Indeterminate Function RW WO Transmit data Nothing is assigned. When write, set to “0”. When read, its content is indeterminate. NOTES: 1. When transfer data length is 9-bit long, write high-byte first then low-byte. 2. Use MOV instruction to write to this register.
R8C/10 Group 13.
R8C/10 Group 13.
R8C/10 Group 13.1 Clock Synchronous Serial I/O Mode 13.1 Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. This mode can be selected with UART0. Table 13.1 lists the specifications of the clock synchronous serial I/O mode. Table 13.2 lists the registers used in clock synchronous serial I/O mode and the register values set. Table 13.
R8C/10 Group 13.1 Clock Synchronous Serial I/O Mode Table 13.
R8C/10 Group 13.
R8C/10 Group 13.1 Clock Synchronous Serial I/O Mode 13.1.1 Polarity Select Function Figure 13.7 shows the polarity of the transfer clock. Use the CKPOL bit in the U0C0 register to select the transfer clock polarity.
R8C/10 Group 13.1 Clock Synchronous Serial I/O Mode 13.1.3 Continuous Receive Mode The unit is configured to continuous receive mode by setting the U0RRM bit in the UCON register to “1” (enabling continuous receive mode). In this mode, reading the U0RB register sets the TI bit in the U0C1 register to “0”(data in the U0TB register). When the U0RRM bit is set to “1”, do not write dummy data to tge U0TB register in a program. Rev.1.
R8C/10 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode 13.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data format. Tables 13.4 lists the specifications of the UART mode. Table 13.5 lists the registers and settings for UART mode. Table 13.
R8C/10 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode Table 13.
R8C/10 Group 13.
R8C/10 Group 13.
R8C/10 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode 13.2.3 Bit Rate Divided-by-16 of frequency by the UiBRG (i=0 to 1) register in UART mode is a bit rate.
R8C/10 Group 14. A/D Converter 14. A/D Converter The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling amplifier. The analog inputs share the pins with P00 to P07. Therefore, when using these pins, make sure the corresponding port direction bits are set to “0” (input mode).
R8C/10 Group 14. A/D Converter CKS1=1 φAD CKS0=1 fAD 1/2 1/2 CKS0=0 AVSS VCUT=1 CKS1=0 A/D conversion rate selection Resistor ladder VREF VCUT=0 Successive conversion register ADCON0 AD register Vcom Decoder Data bus VIN P07/AN0 P06/AN1 P05/AN2 P04/AN3 P03/AN4 P02/AN5 P01/AN6 P00/AN7 CH2,CH1,CH0=0002 CH2,CH1,CH0=0012 CH2,CH1,CH0=0102 CH2,CH1,CH0=0112 CH2,CH1,CH0=1002 CH2,CH1,CH0=1012 CH2,CH1,CH0=1102 CH2,CH1,CH0=1112 CH0 to CH2: Bits in ADCON0 register Figure 14.
14.
14. A/D Converter R8C/10 Group AD control register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 Symbol Address After reset ADCON2 00D416 0016 Bit symbol SMP (b3-b1) (b7-b4) Bit name Function 0 : Without sample and hold 1 : With sample and hold AD conversion method select bit Reserved bit Set to “0” RW RW RW Nothing is assigned. When write, write “0”. When read, its content is “0”. NOTES: 1. If the ADCON2 register is rewritten during A/D conversion, the conversion result is indeterminate.
R8C/10 Group 14.1 One-shot Mode 14.1 One-shot Mode In one-shot mode, the input voltage on one selected pin is A/D converted once. Table 14.2 lists the specifications of one-shot mode. Figure 14.4 shows the ADCON0 and ADCON1 registers in one-shot mode. Table 14.2 One-shot Mode Specifications Item Specification Function Input voltage on one pin selected by CH2 to CH0 bits is A/D converted once.
R8C/10 Group 14.2 Repeat Mode 14.2 Repeat Mode In repeat mode, the input voltage on one selected pin is A/D converted repeatedly. Table 14.3 lists the specifications of repeat mode. Figure 14.5 shows the ADCON0 and ADCON1 registers in repeat mode. Table 14.
R8C/10 Group 14.3 Sample & Hold/14.4 A/D conversion cycles 14.3 Sample and Hold If the SMP bit in the ADCON2 register is set to “1” (with sample-and-hold), the conversion speed per pin is increased to 28 ØAD cycles for 8-bit resolution or 33 ØAD cycles for 10-bit resolution. Sampleand-hold is effective in all operation modes. Select whether or not to use the sample-and-hold function before starting A/D conversion.
R8C/10 Group 14.5 Internal Equivalent Circuit of Analog Input 14.5 Internal Equivalent Circuit of Analog Input Figure 14.8 shows the internal equivalent circuit of analog input. VCC VCC VSS AVCC ON resistor ON resistor approx. 0.6kΩ approx. 2kΩ Wiring resistor C = Approx.1.5pF approx. 0.2kΩ Analog input voltage AMP Parasitic diode AN0 SW1 SW2 Parasitic diode VIN Sampling control signal i ladder-type i ladder-type switches wiring resistors (i = 10) (i = 10) VSS i =10 ON resistor approx.
R8C/10 Group 14.6 Inflow Current Bypass Circuit 14.6 Inflow Current Bypass Circuit Figure 14.9 shows the configuration of the inflow current bypass circuit, figure 14.10 shows the example of an inflow current bypass circuit where VCC or more is applied. OFF OFF Fixed to GND level Unselected channel ON To the internal logic of the A/D Converter ON External input latched into ON Selected channel OFF Figure 14.
R8C/10 Group 14.7 Output Impedance of Sensor under A/D Conversion 14.7 Output Impedance of Sensor under A/D Conversion To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 14.11 has to be completed within a specified period of time. T (sampling time) as the specified time.
R8C/10 Group 14.7 Output Impedance of Sensor under A/D Conversion Microcomputer Sensor equivalent circuit R0 R (2.8 kΩ) VIN C (6 pF) VC NOTE: 1. The capacity of the terminal is assumed to be 4.5 pF. Figure 14.11 Analog Input Pin and External Sensor Equivalent Circuit Rev.1.
R8C/10 Group 15. Programmable I/O Ports 15. Programmable I/O Ports 15. 1 Description The programmable input/output ports (hereafter referred to as “I/O ports”) consist of 22 lines P0, P1, P30 to P33, P37, and P45. Each port can be set for input or output every line by using a direction register, and can also be chosen to be or not be pulled high every 4 lines. The port P1 allows the drive capacity of its Nchannel output transistor to be set as necessary.
R8C/10 Group 15. Programmable I/O Ports P00 to P07 Pull-up selection Direction register Data bus Port latch (Note 1) A/D input P10 to P13, P15 Pull-up selection Direction register Data bus Port latch (Note 1) Select drive capacity Input to respective peripheral functions P14 Pull-up selection Direction register "1" Output Data bus Port latch (Note 1) Select drive capacity NOTES: 1. symbolizes a parasitic diode. Make sure the input voltage on each pin will not exceed Vcc. Figure 15.
R8C/10 Group 15. Programmable I/O Ports P16, P17 Pull-up selection Direction register "1" Output Port latch Data bus (Note 1) Select drive capacity Input to respective peripheral functions P30, P31 Pull-up selection Direction register "1" Output Data bus Port latch (Note 1) NOTES: 1. symbolizes a parasitic diode. Make sure the input voltage on each pin will not exceed Vcc. Figure 15.2 Programmable I/O Ports (2) Rev.1.
R8C/10 Group 15. Programmable I/O Ports P32, P37 Pull-up selection Direction register "1" Output Data bus Port latch (Note 1) Input to respective peripheral functions P33 Pull-up selection Direction register Data bus Port latch (Note 1) Input to respective peripheral functions Digital filter Pull-up selection P45 Direction register Data bus Port latch (Note 1) Input to respective peripheral functions Digital filter NOTES: 1. symbolizes a parasitic diode.
R8C/10 Group 15. Programmable I/O Ports P46/XIN Data bus (Note 3) Clocked inverter(1) (Note 2) P47/XOUT Data bus NOTES: 1. When CM05=1, CM10=1, or CM13=0, the clocked inverter is cutoff. 2. When CM10=1 or CM13=0, the feedback resistor is unconnected. 3. symbolizes a parasitic diode. Make sure the input voltage on each pin will not exceed Vcc. Figure 15.4 Programmable I/O Port (4) MODE MODE signal input (Note 1) CNVSS CNVSS signal input (Note 1) RESET RESET signal input (Note 1) NOTES: 1.
R8C/10 Group 15.
R8C/10 Group 15. Programmable I/O Ports Pull-up control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR0 Address 00FC16 Bit symbol Bit name After reset 00XX00002 Function PU00 P00 to P03 pull-up(1) PU01 P04 to P07 pull-up(1) PU02 P10 to P13 pull-up(1) PU03 P14 to P17 pull-up(1) (b5-b4) Nothing is assigned. When write, set to “0”. When read, its content is indeterminate.
R8C/10 Group 15. Programmable I/O Ports 15.2 Port setting Table 15.1 to Table 15.23 list the port setting. Table 15.
R8C/10 Group 15. Programmable I/O Ports Table 15.5 Port P04/AN3 Setting Register Bit PD0 PUR0 ADCON0 PD0_4 PU01 CH2, CH1, CH0 0 0 XXX 0 1 XXX Setting value 0 0 0112 1 X XXX Function Input port (not pulled up) Input port (pulled up) A/D input (AN3) Output port X: “0” or “1” Table 15.
R8C/10 Group 15. Programmable I/O Ports _____ Table 15.9 Port P10/KI0 Setting Register Bit PD1 PUR0 DRR KIEN P1 PD1_0 PU02 DRR0 KI0EN P1_0 0 0 X X X 0 1 X X X Setting value 0 0 X 1 X 1 X 0 X X 1 X 1 X X Function Input port (not pulled up) Input port (pulled up) _____ KI0 input Output port Output port (High drive) X: “0” or “1” _____ Table 15.
R8C/10 Group 15. Programmable I/O Ports Table 15.
R8C/10 Group 15. Programmable I/O Ports _______ Table 15.16 Port P17/INT1/CNTR0 Setting Register Bit PD1 PUR0 DRR TXMR PD1_7 PU03 DRR5 TXMOD1, TXMOD0 0 0 X Other than 012 0 1 X Other than 012 0 0 X Other than 012 Setting value 1 X 0 Other than 012 1 X 1 Other than 012 X X 0 012 X X 1 012 Function Input port (not pulled up) Input port (pulled up) _______ CNTR0/INT1 input Output port Output port (High drive) CNTR0 output CNTR0 (High drive) X: “0” or “1” ____________ Table 15.
R8C/10 Group 15. Programmable I/O Ports _______ Table 15.20 Port P33/INT3/TCIN Setting Register Bit PD3 PUR0 PD3_3 PU06 0 0 Input port (not pulled up) 0 1 Input port (pulled up) _______ Setting value 0 0 TCIN/INT3 input 1 X Output port Function X: “0” or “1” Table 15.
R8C/10 Group 15. Programmable I/O Ports 15.3 Unassigned Pin Handling Table 15.24 lists the handling of unassigned pins. Table 15.
R8C/10 Group 16. Electrical Characteristics 16. Electrical Characteristics Table 16.1 Absolute Maximum Ratings Condition Rated value Unit VCC Symbol Supply voltage Parameter VCC=AVCC -0.3 to 6.5 V AVCC Analog supply voltage VCC=AVCC -0.3 to 6.5 V VI Input voltage -0.3 to VCC+0.3 V VO Output voltage -0.3 to VCC+0.3 V Pd Power dissipation 300 mW Topr Operating ambient temperature -20 to 85 / -40 to 85 (D version) C Tstg Storage temperature Topr=25 C C -65 to 150 Table 16.
R8C/10 Group 16. Electrical Characteristics Table 16.3 A/D Conversion Characteristics Symbol Parameter – Resolution – Absolute accuracy Standard Unit Min. Typ. Max. Measuring condition Vref =VCC 10 Bit 10 bit mode øAD=10 MHz, Vref=Vcc=5.0V ±3 LSB 8 bit mode øAD=10 MHz, Vref=Vcc=5.0V ±2 LSB 10 bit mode øAD=10 MHz, Vref=Vcc=3.3V(3) ±5 LSB 8 bit mode øAD=10 MHz, Vref=Vcc=3.
R8C/10 Group 16. Electrical Characteristics P0 P1 30pF P2 P3 P4 Figure 16.1 Port P0 to P4 measurement circuit Erase-suspend request (interrupt request) FMR46 td(SR-ES) Figure 16.2 Time delay from Suspend Request until Erase Suspend Rev.1.
R8C/10 Group 16. Electrical Characteristics Table 16.6 Electrical Characteristics (1) [Vcc=5V] Measuring condition Parameter Symbol "H" output voltage Except XOUT IOH=-5mA IOH=-200µA XOUT Drive capacity HIGH Drive capacity LOW VOH "L" output voltage IOH=-1 mA IOH=-500µA Standard Typ. Max. VCC-2.0 VCC-0.3 VCC-2.0 VCC-2.0 Unit VCC VCC VCC VCC V V 2.0 V V V Except P10 to P17, XOUT IOL= 5 mA IOL= 200 µA 0.45 V P10 to P17 Drive capacity HIGH IOL= 15 mA 2.
R8C/10 Group 16. Electrical Characteristics Table 16.
R8C/10 Group 16. Electrical Characteristics Timing requirements (Unless otherwise noted: VCC = 5V, VSS = 0V at Topr = 25 °C) [VCC=5V] Table 16.8 XIN input Symbol tC(XIN) tWH(XIN) tWL(XIN) Parameter XIN input cycle time XIN input HIGH pulse width XIN input LOW pulse width Standard Min. Max. 62.5 – 30 – 30 – Unit Standard Min. Max. 100 – 40 – 40 – Unit Standard Max. Min. 400(1) – 200(2) – 200(2) – Unit ns ns ns ________ Table 16.
R8C/10 Group 16. Electrical Characteristics VCC = 5V tc(CNTR0) tWH(CNTR0) CNTR0 input tWL(CNTR0) tc(TCIN) tWH(TCIN) TCIN input tWL(TCIN) tc(XIN) tWH(XIN) XIN input tWL(XIN) tc(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TxDi td(C-Q) tsu(D-C) RxDi tW(INL) INTi tW(INH) Figure 16.3 Vcc=5V timing diagram Rev.1.
R8C/10 Group 16. Electrical Characteristics Table 16.13 Electrical Characteristics (3) Symbol [Vcc=3V] Measuring condition Parameter "H" output voltage VOH "L" output voltage VOL Except XOUT IOH=-1mA XOUT Drive capacity HIGH Drive capacity LOW Except P10 to P17, XOUT IOL= 1 mA P10 to P17 Drive capacity HIGH XOUT Drive capacity HIGH Drive capacity LOW Drive capacity LOW VT+-VT- Hysteresis II H "H" input current IOH=-0.1 mA IOH=-50 µA VCC-0.5 VCC-0.
R8C/10 Group 16. Electrical Characteristics Table 16.14 Electrical Characteristics (4) Symbol [Vcc=3V] Measuring condition Parameter 5 XIN=16 MHz (square wave) On-chip oscillator on=125 kHz Division by 8 2 .5 XIN=10 MHz (square wave) On-chip oscillator on=125 kHz Division by 8 1 .
R8C/10 Group 16. Electrical Characteristics Timing requirements (Unless otherwise noted: VCC = 3V, VSS = 0V at Topr = 25 °C) [VCC=3V] Table 16.15 XIN input Symbol tC(XIN) tWH(XIN) tWL(XIN) Parameter XIN input cycle time XIN input HIGH pulse width XIN input LOW pulse width Standard Min. Max. 100 – 40 – 40 – Unit Standard Min. Max. 300 – 120 – 120 – Unit Standard Min. Max. 1200(1) – 600(2) – 600(2) – Unit ns ns ns ________ Table 16.
R8C/10 Group 16. Electrical Characteristics VCC = 3V tc(CNTR0) tWH(CNTR0) CNTR0 input tWL(CNTR0) tc(TCIN) tWH(TCIN) TCIN input tWL(TCIN) tc(XIN) tWH(XIN) XIN input tWL(XIN) tc(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TxDi td(C-Q) tsu(D-C) RxDi tW(INL) INTi tW(INH) Figure 16.4 Vcc=3V timing diagram Rev.1.
R8C/10 Group 17. Memory Map 17. Flash Memory Version 17.1 Overview The flash memory version has two modes—CPU rewrite and standard serial I/O—in which its flash memory can be operated on. Table 17.1 outlines the performance of flash memory version (see “Table 1.1 Performance” for the items not listed on Table 17.1). Table 17.1 Flash Memory Version Performance Item Specification Flash memory operating mode 2 modes (CPU rewrite and standard serial I/O) Erase block See “Figure 17.1.
R8C/10 Group 17. Flash Memory Version 17.2 Memory Map The ROM in the flash memory version is separated between a user ROM area and a boot ROM area (reserved area). Figure 17.1 shows the block diagram of flash memory. The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite and standard serial I/O modes. Block 1 and Block 0 are enabled for rewrite in CPU rewrite mode by setting the FMR02 bit in the FMR0 register to “1” (rewrite enabled).
17.3 Functions to Prevent Flash Memory from Rewriting R8C/10 Group 17.3 Functions To Prevent Flash Memory from Rewriting To prevent the flash memory from being read or rewritten easily, standard serial I/O mode has an ID code check function. 17.3.1 ID Code Check Function Use this function in standard serial I/O mode. Unless the flash memory is blank, the ID codes sent from the programmer and the ID codes written in the flash memory are compared to see if they match.
17.4 CPU Rewrite Mode R8C/10 Group 17.4 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted onboard without having to use a ROM programmer, etc. Make sure the Program and the Block Erase commands are executed only on each block in the user ROM area.
17.4 CPU Rewrite Mode R8C/10 Group 17.4.1 EW0 Mode The microcomputer is placed in CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register's FMR11 bit = 0, EW0 mode is selected. Use software commands to control program and erase operations. Read the FMR0 register or status register to check the status of program or erase operation at completion.
17.4 CPU Rewrite Mode R8C/10 Group Figure 17.3 shows the FMR0 register. Figure 17.4 shows the FMR1 and FMR4 registers. • FMR00 Bit This bit indicates the operating status of the flash memory. The bit is “0” during programming, erasing, or erase-suspend mode; otherwise, the bit is “1”. • FMR01 Bit The microcomputer is made ready to accept commands by setting the FMR01 bit to “1” (CPU rewrite mode).
17.
17.4 CPU Rewrite Mode R8C/10 Group Flash memory control register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol Address After reset FM R 1 01B516 0100XX0X2 0 Bit name Bit symbol Reserved bit (b0) Function RW When read, its content is indeterminate. 0: EW0 mode 1: EW1 mode RW RO FMR11 EW1 mode select bit(1) (b3-b2) Reserved bit When read, its content is indeterminate. RO (b5-b4) Reserved bit Set to “0” RW Set to “0” RW (b6) Nothing is assigned. When write, set to “0”.
17.4 CPU Rewrite Mode R8C/10 Group Figures 17.5 shows the timing on suspend operation. Erase Starts Erase Suspends Erase Starts During Erase Erase Ends During Erase FMR00 FMR46 Check that the FMR00 bit is set to “0”, and that the erase operation has not ended. Check the status, and that the program ends normally. Figure 17.5 Timing on Suspend Operation Figures 17.6 and 17.7 show the setting and resetting of EW0 mode and EW1 mode, respectively.
17.4 CPU Rewrite Mode R8C/10 Group On-chip oscillator mode (main clock stop) program Transfer an on-chip oscillator mode (main clock stop)program to any area other the flash memory Jump to the on-chip oscillator mode (main clock stop) program which has been transferred to any area other the flash memory. (The subsequent processing is executed by a program in any area other than the flash memory.
17.4 CPU Rewrite Mode R8C/10 Group 17.4.3 Software Commands Software commands are described below. The command code and data must be read and written in 8-bit units. Table 17.
17.4 CPU Rewrite Mode R8C/10 Group • Program This command writes data to the flash memory in one byte units. Write ‘4016’ in the first bus cycle and write data to the write address in the second bus cycle, and an auto program operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the same address as the write address specified in the second bus cycle. Check the FMR00 bit in the FMR0 register to see if auto programming has finished.
17.4 CPU Rewrite Mode R8C/10 Group • Block Erase Write ‘2016’ in the first bus cycle and write ‘D016’ to the given address of a block in the second bus cycle, and an auto erase operation (erase and verify) will start. Check the FMR00 bit in the FMR0 register to see if auto erasing has finished. The FMR00 bit is “0” during auto erasing and set to “1” when auto erasing is completed. Check the FMR07 bit in the FMR0 register after auto erasing has finished, and the result of auto erasing can be known.
17.4 CPU Rewrite Mode R8C/10 Group Start Interrupt(1, 2) FMR40=1 FMR40=1 Write the command code ‘2016’ Write ‘D016’ to the any block address FMR46=1? NO YES Access to flash memory NO FMR00=1? FMR41=0 YES Full status check REIT Block erase completed Start Interrupt(2) FMR40=1 Access to flash memory Write the command code ‘2016’ REIT Write ‘D016’ to the any block address FMR41=0 FMR00=1? NO YES Full status check Block erase completed NOTES: 1.
17.4 CPU Rewrite Mode R8C/10 Group 17.4.4 Status Register The status register indicates the operating status of the flash memory and whether an erase or programming operation terminated normally or in error. The status of the status register can be known by reading the FMR00, FMR06, and FMR07 bits in the FMR0 register. Table 17.5 lists the status register.
17.4 CPU Rewrite Mode R8C/10 Group 17.4.5 Full Status Check When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating occurrence of each specific error. Therefore, execution results can be verified by checking these status bits (full status check). Table 17.6 lists errors and FMR0 register status. Figure 17.12 shows a full status check flowchart and the action to be taken when each error occurs. Table 17.
17.
R8C/10 Group 17.5 Standard Serial I/O Mode 17.5 Standard Serial I/O Mode In standard serial I/O mode, the user ROM area can be rewritten while the microcomputer is mounted onboard by using a serial programmer suitable for this microcomputer. Standard serial I/O mode has standard serial I/O mode 1 of the clock synchronous serial and standard serial I/O mode 2 of the clock asynchronous serial. Refer to "Appendix 2 Connecting Examples for Serial Writer and On-chip Debugging Emulator".
R8C/10 Group 17.5 Standard Serial I/O Mode Table 17.7 Pin Functions (Flash Memory Standard Serial I/O Mode) Name P in VCC,VSS RESET Apply the voltage guaranteed for Program and Erase to Vcc pin and 0V to Vss pin. Power input IVCC IVCC Reset input Description I/O Connect capacitor (0.1 µF) to Vss. I I Reset input pin. Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins in standard serial I/O mode 2.
R8C/10 Group 17.5 Standard Serial I/O Mode 24 23 22 21 20 19 18 17 25 26 27 MODE 16 15 14 28 29 30 R8C/10 31 32 TxD 13 12 11 Vss 10 9 1 2 3 4 5 6 7 8 Vcc MODE RxD Voltage from programmer RESET Vss -->Vcc R xD CNVss Value Voltage from programmer Voltage from programmer NOTES: 1. No need to connect an oscillation circuit when operating with on-chip oscillator clock. CNVss Mode Setting Signal RESET Connect oscillator circuit(1) Package: PLQP0032GB-A (32P6U-A) Figure 17.
R8C/10 Group 17.5 Standard Serial I/O Mode • Example of Circuit Application in the Standard Serial I/O Mode Figures 17.14 and 17.15 show examples of circuit application in standard serial I/O mode 1 and mode 2, respectively. Refer to the serial programmer manual of your programmer to handle pins controlled by the programmer.
R8C/11 Group 18. On-chip Debugger 18. On-chip debugger The microcomputer has functions to execute the on-chip debugger. Refer to "Appendix 2 Connecting examples for serial writer and on-chip debugging emulator". Refer to the respective on-chip debugger manual for the details of the on-chip debugger. Next, here are some explanations for the respective functions. Debugging the user system which uses these functions is not available.
R8C/10 Group 19. Usage Notes 19. Usage Notes 19.1 Stop Mode and Wait Mode 19.1.1 Stop Mode When entering stop mode, set the CM10 bit to “1” (stop mode) after setting the FMR01 bit to “0” (CPU rewrite mode disabled). The instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit in the CM1 register to “1” (stop mode) and the program stops. Insert at least 4 NOP instructions after inserting the JMP.B instruction immediately after the instruction which sets the CM10 bit to “1”.
R8C/10 Group 19. Usage Notes 19.2 Interrupt 19.2.1 Reading Address 0000016 Do not read the address 0000016 by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 0000016 in the interrupt sequence. At this time, the acknowledged interrupt IR bit is set to “0”. If the address 0000016 is read by a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to “0”.
R8C/10 Group 19. Usage Notes 19.2.5 Changing Interrupt Factor The IR bit in the interrupt control register may be set to “1” (interrupt requested) when the interrupt factor is changed. When using an interrupt, set the IR bit to “0” (interrupt not request) after changing the interrupt factor. In addition, the changes of interrupt factors include all elements that change the interrupt factors assigned to individual software interrupt numbers, polarities, and timing.
R8C/10 Group 19. Usage Notes 19.2.6 Changing Interrupt Control Register (1) Each interrupt control register can only be changed while interrupt requests corresponding to that register are not generated. If interrupt requests may be generated, disable the interrupts before changing the interrupt control register. (2) When changing any interrupt control register after disabling interrupts, be careful with the instruction to be used.
R8C/10 Group 19. Usage Notes 19.3 Clock Generation Circuit 19.3.1 Oscillation Stop Detection Function Since the oscillation stop detection function cannot be used if the main clock frequency is below 2MHz, set the OCD1 to OCD0 bits to “002” (oscillation stop detection function disabled). 19.3.2 Oscillation Circuit Constants Ask the maker of the oscillator to specify the best oscillation circuit constants on your system. Rev.1.
R8C/10 Group 19. Usage Notes 19.4 Timers 19.4.1 Timers X, Y and Z (1) Timers X, Y and Z stop counting after reset. Therefore, a value must be set to these timers and prescalers before starting counting. (2) Even if the prescalers and timers are read out simultaneously in 16-bit units, these registers are read byte-by-byte in the microcomputer. Consequently, the timer value may be updated during the period these two registers are being read. 19.4.
R8C/10 Group 19. Usage Notes 19.5 Serial Interface (1) When reading data from the UiRB (i=0,1) register even in the clock asynchronous serial I/O mode or in the clock synchronous serial I/O mode. Be sure to read data in 16-bit unit. When the high-byte of the UiRB register is read, the PER and FER bits of the UiRB register and the RI bit of the UiC1 register are set to "0". Example (when reading receive buffer register): MOV.
R8C/10 Group 19. Usage Notes 19.6 A/D Converter (1) When writing to each bit but except bit 6 in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit in the ADCON2 register, A/D conversion must be stopped (before a trigger occurs). When the VCUT bit in the ADCON1 register is changed from “0” (VREF not connected) to “1” (VREF connected), wait at least 1 µs before starting A/D conversion. (2) When changing AD operation mode, select an analog input pin again.
R8C/10 Group 19. Usage Notes 19.7 Flash Memory Version 19.7.1 CPU Rewrite Mode ● Operation Speed Before entering CPU rewrite mode (EW0 mode, EW1 mode), select 5MHz or below for the CPU clock using the CM06 bit in the CM0 register and the CM16 to CM17 bits in the CM1 register. ● Instructions Diabled Against Use The following instructions cannot be used in EW0 mode because the flash memory internal data is referenced: UND, INTO and BRK instructions.
R8C/10 Group 19. Usage Notes ● Interrupt Table 19.1 list the Interrupt in EW0 Mode and Table 19.2 lists the Interrupt in EW1 Mode. Table 19.
R8C/10 Group 19. Usage Notes Table 19.2 Interrupt in EW1 Mode Mode EW1 Status During automatic erasing (erase-suspend function is enabled) During automatic erasing (erase-suspend function is disabled) Auto programming When maskable interrupt request is acknowledged The auto-erasing is suspended and the interrupt process is executed.
R8C/10 Group 19. Usage Notes 19.8 Noise (1) Bypass Capacitor between VCC and VSS Pins Insert a bypass capacitor (at least 0.1 µF) between VCC and VSS pins as the countermeasures against noise and latch-up. The connecting wires must be the shortest and widest possible. (2) Port Control Registers Data Read Error During severe noise testing, mainly power supply system noise, and introduction of external noise, the data of port related registers may changed.
R8C/10 Group 20. Usage Notes for On-chip Debugger 20. Usage notes for on-chip debugger When using the on-chip debugger to develop the R8C/10 group program and debug, pay the following attention. (1) Do not use P00/AN7/TxD11 pin and P37/TxD10/RxD1 pin. (2) When write in the PD3 register (00E716 address), set bit 7 to "0". (3) Do not access the related serial interface 1 register. (4) Do not use from OC00016 address to OC7FF16 address because the on-chip debugger uses these addresses.
R8C/10 Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code P-LQFP32-7x7-0.80 RENESAS Code PLQP0032GB-A Previous Code 32P6U-A MASS[Typ.] 0.2g HD *1 D 24 17 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 16 25 bp c c1 HE *2 E b1 Reference Symbol 9 1 ZE Terminal cross section 32 8 ZD c A A1 F A2 Index mark L D E A2 HD HE A A1 bp b1 c c1 L1 y e Rev.1.
Appendix 2. Connecting Examples for Serial Writer and On-chip Debugging Emulator R8C/10 Group Appendix 2. Connecting examples for serial writer and on-chip debugging emulator Appendix figure. 2.1 shows connecting examples with USB Flash Writer and appendix figure 2.2 shows connecting examples with M16C Flash Starter.
Appendix 2. Connecting Examples for Serial Writer and On-chip Debugging Emulator R8C/10 Group Appendix figure 2.3 shows connecting examples with emulator E7. 24 23 22 21 20 19 18 17 25 26 27 28 29 30 31 32 MODE TxD R8C/10 16 15 14 13 12 11 10 9 Vss 1 2 3 4 5 6 7 8 14 13 RESET 12 11 RxD 10 8 7 MODE 6 5 4 TxD Connect oscillator circuit(1) 1 2 V ss CNVss User reset signal CNVss Emulator E7 (HS0007TCU01H) RxD Vcc Vcc NOTES: 1.
R8C/10 Group Appendix 3. Package Dimensions Appendix 3. Example of Oscillation Evaluation Circuit Appendix Figure 3.1 shows the Example of Oscillation Evaluation Circuit. 24 23 22 21 20 19 18 17 0.1µF 25 26 27 28 R8C/10 Group 16 15 14 13 29 30 12 11 31 32 10 9 1 2 3 4 5 6 7 8 RESET Connect oscillation circuit NOTES: 1. Set a program before evaluating. Appendix figure 3.1 Example of Oscillation Evaluation Circuit Rev.1.
R8C/10 Group Register Index Register Index A AD 107 ADCON0 106, 108, 109 ADCON1 106, 108, 109 ADCON2 107 ADIC 39 AIER 52 C CM0 19 CM1 19 PD4 120 PM0 31 PM1 31 PRCR 30 PREX 57 PREY 66 PREZ 74 PUM 67, 69, 71, 75, 77, 79, 81, 84 PUR0 121 PUR1 121 R D DRR 121 RMAD0 52 RMAD1 52 F S FMR0 146 FMR1 147 FMR4 147 S0RIC S0TIC S1RIC S1TIC I INT0F INT0IC INT1IC INT2IC INT3IC INTEN T 46 39 39 39 39 46 TC 87 TCC0 49, 87 TCC1 49, 87 TCIC 39 TCSS 57, 67, 75 TM0 87 TX 57 TXIC 39 TXMR 48, 56, 58, 59, 60, 61, 63
R8C/10 Group TZSC Register Index 74 U U0BRG 91 U0C0 92 U0C1 93 U0MR 92 U0RB 91 U0TB 91 U1BRG 91 U1C0 92 U1C1 93 U1MR 92 U1RB 91 U1TB 91 UCON 93 W WDC 54 WDTR 54 WDTS 54 Rev.1.
R8C/10 Group Hardware Manual REVISION HISTORY Rev. Date Description Summary Page 0.91 Sep 8, 2003 0.92 Nov 5, 2003 – First edition issued 2 Table1.1 Add on Power Consumption Internal : Revise 10 sources to 9 sources 4 Table 1.2 Delete ** 6 Table1.3 CNVss and MODE : Delete (5 kΩ) CNVss : Add NOTES 1 Analog power supply input : Add one sentence Reference voltage input : Add one sentence 14 Section 5.1 Add one sentence Section 5.2 Add one sentence Delete sentences Section 5.
R8C/10 Group Hardware Manual REVISION HISTORY Rev. Date Description Summary Page 0.92 Nov 5, 2003 84 Table 12.12 revised 87 Figure 12.28 Add “Sampling clock” 101 Table 13.5 110 Section 14.3 Add under the sixth line Add Figure 14.6 116 Figure 15.6 Figure 15.7 Add bit “CKPOL”, “Set to “0”” NOTES 2 and 3 : Revise its content is “0” to its content is indetermi nate NOTES 1 and 2 : Revise its content is “0” to its content is indetermi nate 119 Table 16.2 120 Table 16.
R8C/10 Group Hardware Manual REVISION HISTORY Rev. Date 0.92 Nov 5, 2003 Section 17.5 Description Summary Add sentences 148 Table 17.7 Revise P46/XIN and P47/XOUT 150 Figure 17.13 Figure 17.14 Add NOTES 3 Add NOTES 2 155 Section 19.3.2 Add (1) and (4) Add Section 19.3.3 (1) Revise 19.3.3 Timer Z to 19.3.4 Timer ZSection 19.3.3 Add (1) 161 Section 20 Page 147 0.93 Feb 18, 2004 147- 150 1.
R8C/10 Group Hardware Manual REVISION HISTORY Rev. Date Description Summary Page 1.00 Sep 24, 2004 Table 12.9 revised Table 12.10 revised, NOTES revised Table 12.11 revised, NOTES revised Figure 12.25 revised Table 12.12 revised, NOTES revised Figure 12.27 revised Figure 12.29 revised Figure 13.2 revised 13.1.3 revised Figure 13.10 revised Figure numbers in 15.1.1, 15.1.2, 15.1.3 and 15.1.4 revised Table 15.1 revised Table 16.2 revised Table 16.3 revised Table 16.4 revised Table 16.
R8C/10 Group Hardware Manual REVISION HISTORY Rev. Date Description Summary Page 1.10 Apr.27.2005 4 5 10 12 14 15 17 19 21 23 24 27 28 54 63 80 83 87 100 103 110 111 112 114 115 116 120-125 126 128 130 134 138 146 149 151 157 159 164 165 167 168 172 173 Table 1.2, Figure 1.2 package name revised Figure 1.3 package name revised Table 4.1 revised Table 4.3 revised 5.1 partly revised Figure 5.2 partly revised Table 6.1 partly added Figure 6.2 partly revised 6.1 partly revised 6.3.1 partly deleted 6.4.
R8C/10 Group Hardware Manual REVISION HISTORY Rev. Date 1.20 Jan.27.2006 Description Page Summary 2 3 4 Table 1.1 Performance outline revised Figure 1.1 Block diagram partly revised 1.4 Product Information, title of Table 1.2 “Product List” → “Product Informaton” revised Figure 1.2 Type No., Memory Size, and Package partly revised Table 1.3 Pin description revised 2 Central Processing Unit (CPU) revised Figure 2.1 CPU register revised Table 4.1 SFR Information(1) NOTES:1 revised Table 4.
R8C/10 Group Hardware Manual REVISION HISTORY Rev. Date 1.20 Jan.27.2006 Description Page Summary 113 116 117 118 119 127 14.7 Output Impedance of Sensor under A/D Conversion added Figure 15.1 Programmable I/O Ports (1); NOTES: 1 added Figure 15.2 Programmable I/O Ports (2); NOTES: 1 added Figure 15.3 Programmable I/O Ports (3); NOTES: 1 added Figure 15.4 Programmable I/O Ports (4); NOTES: 3 added _______ Table 15.20 Port P33/INT 3/TCIN Setting; Bit: “PD3_1” → “PD3_3” _______ Table 15.
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER HARDWARE MANUAL R8C/10 Group Publication Data : Rev.0.93 Feb 18, 2004 Rev.1.20 Jan 27, 2006 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
R8C/10 Group Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan
