Hardware manual

ManualsBrandsRenesas ManualsStereo SystemR8C/25

Rev. 1.1

R8C25 QuickDesign Guide.doc Page 1 of 10 12/23/2007

R8C QuickDesign Guide

Introduction

The purpose of the document is to help the designed get started their design on the

R8C/25 family. This document covers some commonly asked questions and provides

some design tips. The document is not intended to be a replacement for the hardware

manual; it is intended to supplement the manual by highlighting some key items most

engineers will need to start their own design. It also discusses some design decisions

from an application point of view

Contents

1. Power Supplies and Bypassing

2. Memory

a. Memory Access Time

i. Flash

ii. RAM

iii. SFR

3. Reset and Reset Circuit

a. Recommended Reset Circuit

b. State of device during Reset

4. GPIO

a. Protected Ports

b. Pullups

5. Clock circuits

a. On-Chip Oscillator

b. High Speed Crystal

c. Low Speed Crystal

d. Reset State and switching oscillators

6. Interrupts

a. Vector Table

b. Clearing Interrupt Request

c. Key Input Interrupt

Summary of content (10 pages)

PAGE 1
Rev. 1.1 R8C QuickDesign Guide Introduction The purpose of the document is to help the designed get started their design on the R8C/25 family. This document covers some commonly asked questions and provides some design tips. The document is not intended to be a replacement for the hardware manual; it is intended to supplement the manual by highlighting some key items most engineers will need to start their own design. It also discusses some design decisions from an application point of view Contents 1. 2.
PAGE 2
Rev. 1.1 1. Power Supplies and Bypassing 1.1. Operating Frequency The maximum operating frequency for the R8C/25 is dependent on the power supply voltage supplied to the R8C. The electrical characteristics section of the hardware manual defines the maximum frequency vs. voltage. Input Voltage 3.0 VDC ≤ Vcc ≤ 5.5VDC 2.7 VDC ≤ Vcc < 3.0 VDC 2.2 VDC ≤ Vcc < 2.7 VDC Maximum Operating Frequency 20 MHz 10 MHz 5 MHz 1.
PAGE 3
Rev. 1.1 When using the POR feature do not connect a capacitor from the Reset input to Ground or you may have conditions where the POR circuit does not operate properly 3.2. Using RC Reset circuit If the POR feature cannot be used, or is not desired, the MCU can be reliably Reset using an RC circuit connected to the Reset input. In this case the POR feature should be disabled by modifying the setting in the OFS register since the default setting enables the POR feature.
PAGE 4
Rev. 1.1 control the Reset line. The Debugging section of this document provides additional information 3.4. MCU States after Hardware Reset The state of each peripheral after Reset is given in the applicable sections of the HW manual. The Reset condition of each register is also given above the register description. Section 4 of the HW manual , Special Function Registers, provides a single table with all the peripheral register states after Reset.
PAGE 5
Rev. 1.1 • Port 0 direction register is protected from accidental modification. Before modifying this register Bit 2 in the Protect Register (PRCR) must be Set.
PAGE 6
Rev. 1.1 6. Clock Circuits 6.1. Reset Conditions • On Power-Up and after a Reset the MCU will be running on the Slow Speed On-Chip Oscillator with the CPU clock (Bclk) divided by 8. This results in a core clock speed of approximately 125 kHz/8 or 15 kHz. It is, therefore, important to shift to a higher speed clock early in the program if startup time is important • The High Speed On-Chip Oscillator trim register will be loaded with the calibrated value to provide a 40 MHz clock as part of a Reset. 6.2.
PAGE 7
Rev. 1.1 8. Interrupts The R8C has individual interrupts for nearly all peripherals. The interrupts can have individual priorities and separate vector locations for the interrupt service routines. The M16C family, including the R8C, has two interrupt vector tables. One table has fixed addresses which we will refer to as the fixed interrupt table. The other table can be relocated by changing the value of the INTB core register, which is referred to as the relocatable vector table. 8.1.
PAGE 8
Rev. 1.1 normally used, if an ID code is not intentionally written to these locations the ID code will typically be all 00’s or all FF’s 8.2.3. Modifying the Shared Features in Vector Table The High Performance Embedded Workshop IDE has provisions to allow setting both the OSFR register and ID code values. These options can be found by going to the Build >> Renesas M16C Standard Toolchain then LMC tabs. The options will be under the “Code” category. 8.3.
PAGE 9
Rev. 1.1 6. The CPU gets interrupt information (interrupt number and interrupt request level) by reading address 00000h. 7. The IR bit for the corresponding interrupt is set to 0 (interrupt not requested)) 8. The FLG register is saved to a temporary register(1) in the CPU immediately before entering the interrupt sequence. 9. The I, D and U flags in the FLG register are set as follows: • The I flag is set to 0 (interrupts disabled). • The D flag is set to 0 (single-step interrupt disabled).
PAGE 10
Rev. 1.1 • • #pragma INTERRUPT {function declaration} /E The compiler will automatically re-enable interrupts during the ISR to allow nested interrupts You cannot use /B and /E on the same interrupt declaration (you will not get an error it just won’t generate the code for those switches) The IR bit can be cleared by software but cannot be set by software. 8.5.4.