Technical information

R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU)
Rev.2.10 Jan 19, 2006 Page 147 of 253
REJ09B0164-0210
Figure 15.7 SSMR2 Register
SS Mode Register 2
(5)
Symbol Address After Reset
SSMR2
00BDh 00h
Bit Symbol Bit Name Function RW
SCS
_
____
Pin Open Drain Output
0 : CMOS output
Select Bit
1 : NMOS open drain output
SCS
_
____
Pin Select Bit
(2)
b5 b4
0 0 : Functions as port
0 1 : Function as SCS
_
____
input pin
1 0 : Function as SCS
_
____
output pin
(3)
1 1 : Functions as SCS
_
____
output pin
(3)
NOTES :
1.
2.
3.
4.
5. Refer to
20.6.1 Access Registers Associated with SSU
for accessing registers associated with SSU.
RW
b0
Ref er to
15.2 Relationship between Data I/O Pin and SS Shift Register
for the combination of the data
The SCS
_
_____
pin functions as a port, regardless of the contents of the CSS0 and CSS1 bits w hen the SSUMS
SCKS
SSCK Pin Select Bit 0 : Functions as port
1 : Functions as serial clock pin
RW
b3 b2 b1b7 b6 b5 b4
CSS0
CSS1
SOOS
SCKOS
SSUMS
CSOS
RW
0 : Clock Synchronous Communication Mode
1 : Four-Wire Bus Communication Mode
SSCK Pin Open Drain Output
Select Bit
0 : CMOS output
1 : NMOS open drain output
SSU Mode Select Bit
(1)
SSO Pin Open Drain Output
Select Bit
(1)
0 : CMOS output
1 : NMOS open drain output
RW
RW
RW
RW
The BIDE bit is disabled w hen the SSUMS bit is set to “0” (clock synchronous communication mode).
RWBIDE
Bidirectional Mode Enable Bit
(1, 4)
0 : Standard mode (communicates using 2
pins of data input and data output)
1 : Bidirectional mode (communicates using
1 pin of data input and data output)
This bit functions as the SCS
_
____
input pin before starting transfer.
I/O pin.
bit is set to “0” (clock synchronous communication mode).