Technical information

R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU)
Rev.2.10 Jan 19, 2006 Page 144 of 253
REJ09B0164-0210
Figure 15.4 SSMR Register
SS Mode Register
(2)
Symbol Address After Reset
SSMR
00BAh 00011000b
Bit Symbol Bit Name Function RW
Reserved Bit
NOTES :
1.
2.
0 : “H” w hen clock stops
1 : “L” w hen clock stops
Set to “1”.
When read, its content is “1”.
RW
RW
RW
—
RW
0 : Transfers data at MSB first
1 : Transfers data at LSB first
R
BC1
BC2
Bit Counter 2 to 0
b2 b1 b0
0 0 0 : 8-bit left
0 0 1 : 1-bit left
0 1 0 : 2-bit left
0 1 1 : 3-bit left
1 0 0 : 4-bit left
1 0 1 : 5-bit left
1 1 0 : 6-bit left
1 1 1 : 7-bit left
BC0
R
R
MLS
Nothing is assigned. When w rite, set to “0”.
When read, its content is “1”.
—
(b3)
—
(b4)
CPHS
SSCK Clock Phase Select Bit
(1)
0 : Change data at odd edge
(Dow nloads data at even edge)
1 : Change data at even edge
(Dow nloads data at odd edge)
CPOS
SSCK Clock Polarity Select Bit
(1)
b7 b6 b5 b4
Ref er to
15.1.1 Association betw een Transfer Clock Polarity, Phase and Data
for the setting of the CPHS and
CPOS bits .
Ref er to
20.6.1 Access Registers Associated with SSU
for accessing registers associated w ith SSU.
b3 b2 b1 b0
1
MSB First/LSB First Select Bit