Technical information

R8C/14 Group, R8C/15 Group 13. Timers
Rev.2.10 Jan 19, 2006 Page 91 of 253
REJ09B0164-0210
Figure 13.6 TXMR Register in Event Counter Mode
Timer X Mode Register
Symbol Address After Reset
TXMR
008Bh 00h
Bit Symbol Bit Name Function RW
INT1
_
____
/CNTR0 Signal
Polarity Sw itch Bit
(1)
NOTES :
1.
2.
Set to “0” in event counter mode
Ref er to
20.4.2 Timer X
for precautions on the TXS bit.
01
The IR bit in the INT1IC register may be set to “1” (requests interrupt) w hen the R0EDG bit is rew ritten.
Ref er to
20.2.5 Changing Interrupt Factor
.
R0EDG RW
RW
TXOCNT RW
TXMOD0 RWOperating Mode Select Bit 0, 1
b1 b0
1 0 : Event Counter Mode
TXMOD1 RW
b0
0000
b7 b6 b5 b4
RW
b3 b2
0 : Rising edge
1 : Falling edge
TXS
Timer X Count Start Flag
(2)
0 : Stops counting
1 : Starts counting
b1
Set to “0” in event counter mode
Set to “0” in event counter mode
RW
TXUND RW
TXEDG
Set to “0” in event counter modeTXMOD2