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To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both

companies. Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry

Summary of content (279 pages)

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To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
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Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
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Hardware Manual 16 R8C/14 Group, R8C/15 Group Hardware Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / R8C/Tiny SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp.
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
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How to Use This Manual 1. Introduction This hardware manual provides detailed information on the R8C/14 Group, R8C/15 Group of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit function in each register are shown below.
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3. M16C Family Documents The following documents were prepared for the M16C family.(1) Document Short Sheet Data Sheet Hardware Manual Contents Hardware overview Hardware overview and electrical characteristics Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, timing charts). *Refer to the application note for how to use peripheral functions.
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Table of Contents SFR Page Reference 1. 2. 3. B-1 Overview 1 1.1 Applications .................................................................................................1 1.2 Performance Overview................................................................................2 1.3 Block Diagram .............................................................................................4 1.4 Product Information ...............................................................................
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4. Special Function Register (SFR) 15 5. Reset 19 5.1 6. 5.1.1 When the power supply is stable........................................................21 5.1.2 Power on ............................................................................................21 5.2 Power-On Reset Function .........................................................................23 5.3 Voltage Monitor 1 Reset ...........................................................................24 5.
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.4.1 Normal Operating Mode .....................................................................48 9.4.2 Wait Mode ..........................................................................................49 9.4.3 Stop Mode ..........................................................................................51 9.5 Oscillation Stop Detection Function ..........................................................53 9.5.1 How to Use Oscillation Stop Detection Function ...............................
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13.2.2 Programmable Waveform Generation Mode....................................105 13.2.3 Programmable One-shot Generation Mode .....................................108 13.2.4 Programmable Wait One-shot Generation Mode .............................111 13.3 Timer C....................................................................................................115 13.3.1 Input Capture Mode..........................................................................121 13.3.2 Output Compare Mode ..
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16.2 Repeat Mode...........................................................................................174 16.3 Sample and Hold.....................................................................................176 16.4 A/D Conversion Cycles ...........................................................................176 16.5 Internal Equivalent Circuit of Analog Input ..............................................177 16.6 Inflow Current Bypass Circuit ...........................................
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20.2.1 Reading Address 00000h .................................................................236 20.2.2 SP Setting.........................................................................................236 20.2.3 External Interrupt and Key Input Interrupt ........................................236 20.2.4 Watchdog Timer Interrupt.................................................................236 20.2.5 Changing Interrupt Factor.................................................................
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SFR Page Reference Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Register Symbol Page Processor Mode Register 0 Processor Mode Register 1 System Clock Control Reg
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Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh Register Timer Z Mode Register Symbol TZMR Page 99 Timer Z Waveform Output Control Register Prescaler Z Timer Z Seco
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R8C/14 Group, R8C/15 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1. REJ09B0164-0210 Rev.2.10 Jan 19, 2006 Overview This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU core and is packaged in a 20-pin plastic molded LSSOP. This MCU operates using sophisticated instructions featuring a high level of instruction efficiency. With 1 Mbyte of address space, it is capable of executing instructions at high speed.
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R8C/14 Group, R8C/15 Group 1.2 1. Overview Performance Overview Table 1.1 lists the Performance Outline of the R8C/14 Group and Table 1.2 lists the Performance Outline of the R8C/15 Group. Table 1.1 Performance Outline of the R8C/14 Group Item Performance CPU Number of Basic Instructions 89 instructions Minimum Instruction 50ns(f(XIN)=20MHz, VCC=3.0 to 5.5V) Execution Time 100ns(f(XIN)=10MHz, VCC=2.7 to 5.5V) Operating Mode Single-chip Memory Space 1 Mbyte Memory Capacity See Table 1.
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R8C/14 Group, R8C/15 Group Table 1.2 1. Overview Performance Outline of the R8C/15 Group Item Performance CPU Number of Basic Instructions 89 instructions Minimum Instruction 50ns (f(XIN)=20MHz, VCC=3.0 to 5.5V) Execution Time 100ns (f(XIN)=10MHz, VCC=2.7 to 5.5V) Operating Mode Single-chip Memory Space 1 Mbyte Memory Capacity See Table 1.
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R8C/14 Group, R8C/15 Group 1.3 1. Overview Block Diagram Figure 1.1 shows a Block Diagram.
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R8C/14 Group, R8C/15 Group 1.4 1. Overview Product Information Table 1.3 lists the Product Information of R8C/14 Group and Table 1.4 lists the Product Information of R8C/15 Group. Table 1.3 Product Information of R8C/14 Group Type No. R5F21142SP R5F21143SP R5F21144SP R5F21142DSP R5F21143DSP R5F21144DSP Type No.
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R8C/14 Group, R8C/15 Group Table 1.4 1. Overview Product Information of R8C/15 Group Type No. R5F21152SP R5F21153SP R5F21154SP R5F21152DSP R5F21153DSP R5F21154DSP Type No.
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R8C/14 Group, R8C/15 Group 1.5 1. Overview Pin Assignments Figure 1.4 shows the PLSP0020JB-A Package Pin Assignment (top view).
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R8C/14 Group, R8C/15 Group 1.6 1. Overview Pin Description Table 1.5 lists the Pin Description and Table 1.6 lists the Pin Name Information by Pin Number. Table 1.5 Pin Description Function Power Supply Input Pin name I/O type Description I Apply 2.7V to 5.5V to the VCC pin. Apply 0V to the VSS pin Analog Power Supply AVCC Input AVSS I Power supply input pins to A/D converter. Connect AVCC to VCC. Apply 0V to AVSS. Connect a capacitor between AVCC and AVSS.
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R8C/14 Group, R8C/15 Group Table 1.6 Pin Number Pin Name Information by Pin Number Control Pin 1 2 3 4 5 6 7 8 9 1.
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R8C/14 Group, R8C/15 Group 2. 2. Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 2.1 shows the CPU Register. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. Two sets of register banks are provided.
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R8C/14 Group, R8C/15 Group 2.1 2. Central Processing Unit (CPU) Data Registers (R0, R1, R2 and R3) R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers. The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit data register (R2R0). The same applies to R3R1 as R2R0. 2.
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R8C/14 Group, R8C/15 Group 2.8.7 2. Central Processing Unit (CPU) Interrupt Enable Flag (I Flag) The I flag enables a maskable interrupt. An interrupt is disabled when the I flag is set to “0”, and are enabled when the I flag is set to “1”. The I flag is set to “0” when an interrupt request is acknowledged. 2.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is set to “0”, USP is selected when the U flag is set to “1”.
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R8C/14 Group, R8C/15 Group 3. 3. Memory Memory 3.1 R8C/14 Group Figure 3.1 is a Memory Map of R8C/14 Group. The R8C/14 group provides 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses beginning with address 0FFFFh. For example, a 16Kbyte internal ROM is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine.
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R8C/14 Group, R8C/15 Group 3.2 3. Memory R8C/15 Group Figure 3.2 is a Memory Map of R8C/15 Group. The R8C/15 group provides 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine.
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R8C/14 Group, R8C/15 Group 4. 4. Special Function Register (SFR) Special Function Register (SFR) SFR (Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR information. Table 4.
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R8C/14 Group, R8C/15 Group Table 4.2 Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 4.
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R8C/14 Group, R8C/15 Group Table 4.3 Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh 4.
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R8C/14 Group, R8C/15 Group Table 4.4 Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh 4.
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R8C/14 Group, R8C/15 Group 5. 5. Reset Reset There are resets: hardware reset, power-on reset, voltage monitor 1 reset, voltage monitor 2 reset, watchdog timer reset and software reset. Table 5.1 lists the Reset Name and Factor. Table 5.
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R8C/14 Group, R8C/15 Group 5. Reset Table 5.2 shows the Pin Status after Reset, Figure 5.2 shows CPU Register Status after Reset and Figure 5.3 shows Reset Sequence. Table 5.
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R8C/14 Group, R8C/15 Group 5.1 5. Reset Hardware Reset A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the power supply voltage meets the recommended performance condition, the pins, CPU and SFR are reset (refer to Table 5.2 Pin Status after Reset). When the input level applied to the RESET pin changes “L” to “H”, the program is executed beginning with the address indicated by the reset vector.
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R8C/14 Group, R8C/15 Group 5. Reset VCC 2.7V VCC 0V RESET RESET 0.2VCC or below 0V td(P-R)+500µs or above NOTES: 1. Refer to 19. Electrical Characteristics. Figure 5.4 Example of Hardware Reset Circuit and Operation Power Supply Voltage Detection Circuit RESET 5V VCC 2.7V VCC 0V 5V RESET 0V td(P-R)+500µs or above Example when VCC=5V NOTES: 1. Refer to 19. Electrical Characteristics. Figure 5.
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R8C/14 Group, R8C/15 Group 5.2 5. Reset Power-On Reset Function When the RESET pin is connected to the VCC pin via about 5kΩ pull-up resistor and the VCC pin rises, the function is enabled and the microcomputer resets its pins, CPU, and SFR. When a capacitor is connected to the RESET pin, always keep the voltage to the RESET pin 0.8VCC or more. When the input voltage to the VCC pin reaches to the Vdet1 level or above, count operation of the lowspeed on-chip oscillator clock starts.
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R8C/14 Group, R8C/15 Group 5.3 5. Reset Voltage Monitor 1 Reset A reset is applied using the built-in voltage detection 1 circuit. The voltage detection 1 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet1. When the input voltage to the VCC pin reaches to the Vdet1 level or below, the pins, CPU and SFR are reset. And when the input voltage to the VCC pin reaches to the Vdet1 level or above, count operation of the low-speed on-chip oscillator clock starts.
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R8C/14 Group, R8C/15 Group 6. 6. Voltage Detection Circuit Voltage Detection Circuit The voltage detection circuit is a circuit to monitor the input voltage to the VCC pin. This circuit monitors the VCC input voltage by the program. And the voltage monitor 1 reset, voltage monitor 2 interrupt and voltage monitor 2 reset can be used. Table 6.1 lists the Specification of Voltage Detection Circuit and Figures 6.1 to 6.3 show the Block Diagrams. Figures 6.4 to 6.6 show the Associated Registers. Table 6.
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R8C/14 Group, R8C/15 Group 6. Voltage Detection Circuit VCA27 VCC + Internal Reference Voltage - Voltage Detection 2 Signal Noise Filter ≥ Vdet2 VCA1 Register b3 VCA26 VCA13 Bit Voltage Detection 1 Signal + - Figure 6.
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R8C/14 Group, R8C/15 Group 6. Voltage Detection Circuit Voltage Monitor 2 Interrupt / Reset Generation Circuit VW2F1 to VW2F0 =00b =01b Voltage Detection 2 Circuit =10b fRING-S 1/2 1/2 1/2 VW2C2 bit is set to “0” (not detected) by writing “0” by program.
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R8C/14 Group, R8C/15 Group 6. Voltage Detection Circuit Voltage Detection Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 Symbol Address 0031h VCA1 Bit Symbol Bit Name — Reserved Bit (b2-b0) VCA13 — (b7-b4) After Reset(2) 00001000b Function Set to “0” RW RW Voltage Detection 2 Signal Monitor Flag(1) 0 : VCC < Vdet2 1 : VCC ≥ Vdet2 or voltage detection 2 circuit disabled Reserved Bit Set to “0” RO RW NOTES : 1.
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R8C/14 Group, R8C/15 Group 6.
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R8C/14 Group, R8C/15 Group 6.
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R8C/14 Group, R8C/15 Group 6.1 6. Voltage Detection Circuit Monitoring VCC Input Voltage 6.1.1 Monitoring Vdet1 Vdet1 cannot be monitored. 6.1.2 Monitoring Vdet2 Set the VCA27 bit in the VCA2 register to “1” (voltage detection 2 circuit enabled). After td(E-A) (refer to 19. Electrical Characteristics) elapse, Vdet2 can be monitored by the VCA13 bit in the VCA1 register. Rev.2.
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R8C/14 Group, R8C/15 Group 6.2 6. Voltage Detection Circuit Voltage Monitor 1 Reset Table 6.2 lists the Setting Procedure of Voltage Monitor 1 Reset Associated Bit and Figure 6.7 shows the Operating Example of Voltage Monitor 1 Reset. When using the voltage monitor 1 reset to exit stop mode, set the VW1C1 bit in the VW1C register to “1” (digital filter disabled). Table 6.
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R8C/14 Group, R8C/15 Group 6.3 6. Voltage Detection Circuit Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Table 6.3 lists the Setting Procedure of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Associated Bit. Figure 6.8 shows the Operating Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset. When using the voltage monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1 bit in the VW2C register to “1” (digital filter disabled). Table 6.
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R8C/14 Group, R8C/15 Group Vdet2 (Typ. 3.30V) 6. Voltage Detection Circuit VCC 2.
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R8C/14 Group, R8C/15 Group 7. 7. Processor Mode Processor Mode 7.1 Types of Processor Mode Single-chip mode can be selected as processor mode. Table 7.1 lists Features of Processor Mode. Figure 7.1 shows the PM0 Register and Figure 7.2 shows the PM1 Register. Table 7.
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R8C/14 Group, R8C/15 Group 7. Processor Mode Processor Mode Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol PM1 Address 0005h After Reset 00h Bit Symbol Bit Name Nothing is assigned. When w rite, set to “0”. — When read, its content is indeterminate. (b0) — (b1) PM12 — (b6-b3) — (b7) Function Reserved Bit Set to “0” WDT Interrupt/Reset Sw itch Bit 0 : Watchdog Timer Interrupt 1 : Watchdog Timer Reset(2) Nothing is assigned. When w rite, set to “0”. When read, its content is “0”.
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R8C/14 Group, R8C/15 Group 8. 8. Bus Bus During access, the ROM/RAM and SFR vary from bus cycles. Table 8.1 lists Bus Cycles for Access Space of the R8C/14 Group and Table 8.2 lists Bus Cycles for Access Space of the R8C/15 Group. The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word-(16 bits) unit, these area are accessed twice in 8-bit unit. Table 8.3 lists Access Unit and Bus Operation. Table 8.
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R8C/14 Group, R8C/15 Group 9. 9. Clock Generation Circuit Clock Generation Circuit The MCU has two on-chip clock generation circuits: • Main clock oscillation circuit • On-chip oscillator (oscillation stop detection function) Table 9.1 lists Specification of Clock Generation Circuit. Figure 9.1 shows a Clock Generation Circuit. Figures 9.2 to 9.5 show clock-associated registers. Table 9.
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R8C/14 Group, R8C/15 Group 9.
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R8C/14 Group, R8C/15 Group 9.
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R8C/14 Group, R8C/15 Group 9.
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R8C/14 Group, R8C/15 Group 9.
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R8C/14 Group, R8C/15 Group 9.
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R8C/14 Group, R8C/15 Group 9. Clock Generation Circuit High-speed On-Chip Oscillator Control Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol HRA1 Address 0021h After Reset When Shipping Function The frequency of high-speed on-chip oscillator is adjusted w ith bits 0 to 7.
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R8C/14 Group, R8C/15 Group 9. Clock Generation Circuit The following describes the clocks generated by the clock generation circuit. 9.1 Main Clock This clock is supplied by a main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillation circuit is configured by connecting a resonator between the XIN and XOUT pins.
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R8C/14 Group, R8C/15 Group 9.2 9. Clock Generation Circuit On-Chip Oscillator Clock This clock is supplied by an on-chip oscillator. The on-chip oscillator contains a high-speed on-chip oscillator and a low-speed on-chip oscillator. Either an on-chip oscillator clock is selected by the HRA01 bit in the HRA0 register. 9.2.
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R8C/14 Group, R8C/15 Group 9.3 9. Clock Generation Circuit CPU Clock and Peripheral Function Clock There are two type clocks: a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer to Figure 9.1 Clock Generation Circuit. 9.3.1 System Clock The system clock is a clock source for the CPU and peripheral function clocks. The main clock or onchip oscillator clock can be selected. 9.3.
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R8C/14 Group, R8C/15 Group 9.4 9. Clock Generation Circuit Power Control There are three power control modes. All modes other than wait and stop modes are referred to as normal operating mode. 9.4.1 Normal Operating Mode Normal operating mode is further separated into four modes. In normal operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU and the peripheral function clocks. Power consumption control is enabled by controlling the CPU clock frequency.
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R8C/14 Group, R8C/15 Group 9.4.1.1 9. Clock Generation Circuit High-Speed Mode The main clock divided-by-1 (no division) provides the CPU clock. If the CM14 bit is set to “0” (lowspeed on-chip oscillator on) or the HRA00 bit in the HRA0 register is set to “1” (high-speed on-chip oscillator on), the fRING and fRING128 can be used for timers X and C. When the HRA00 bit is set to “1”, fRING-fast can be used for timer C.
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R8C/14 Group, R8C/15 Group 9.4.2.4 9. Clock Generation Circuit Exiting Wait Mode The microcomputer exits wait mode by a hardware reset or peripheral function interrupt. When using a hardware reset to exit wait mode, set the ILVL2 to ILVL0 bits for the peripheral function interrupts to “000b” (interrupts disabled) before executing the WAIT instruction. The peripheral function interrupts are affected by the CM02 bit.
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R8C/14 Group, R8C/15 Group 9.4.3 9. Clock Generation Circuit Stop Mode Since the oscillator circuits stop in wait mode, the CPU clock and peripheral function clock stop and the CPU and peripheral functions clocked by these clocks stop operating. The least power required to operate the microcomputer is in stop mode. If the voltage applied to the VCC pin is VRAM or more, the internal RAM is maintained. The peripheral functions clocked by external signals maintain operating. Table 9.
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R8C/14 Group, R8C/15 Group 9. Clock Generation Circuit Figure 9.8 shows the State Transition of Power Control. Reset There are six power control modes.
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R8C/14 Group, R8C/15 Group 9.5 9. Clock Generation Circuit Oscillation Stop Detection Function The oscillation stop detection function is a function to detect the stop of the main clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by the OCD1 to OCD0 bits in the OCD register. Table 9.5 lists the Specification of Oscillation Stop Detection Function.
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R8C/14 Group, R8C/15 Group Table 9.6 9.
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R8C/14 Group, R8C/15 Group 10. Protection 10. Protection Protection function protects important registers from being easily overwritten when a program runs out of control. Figure 10.1 shows the PRCR Register. The following lists the registers protected by the PRCR register.
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R8C/14 Group, R8C/15 Group 11. Interrupt 11. Interrupt 11.1 Interrupt Overview 11.1.1 Types of Interrupts Figure 11.1 shows types of Interrupts. Software (Non-Maskable Interrupt) Interrupt Special (Non-Maskable Interrupt) Hardware Undefined Instruction (UND Instruction) Overflow (INTO Instruction) BRK Instruction INT Instruction Watchdog Timer Oscillation Stop Detection Voltage Monitor 2 Single Step(2) Address Match Peripheral Function(1) (Maskable Interrupt) NOTES : 1.
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R8C/14 Group, R8C/15 Group 11.1.2 11. Interrupt Software Interrupts A software interrupt is generated when an instruction is executed. The software interrupts are nonmaskable interrupts. 11.1.2.1 Undefined Instruction Interrupt The undefined instruction interrupt is generated when the UND instruction is executed. 11.1.2.2 Overflow Interrupt The overflow interrupt is generated when the O flag is set to “1” (arithmetic operation overflow) and the INTO instruction is executed.
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R8C/14 Group, R8C/15 Group 11.1.3 11. Interrupt Special Interrupts Special interrupts are non-maskable interrupts. 11.1.3.1 Watchdog Timer Interrupt The watchdog timer interrupt is generated by the watchdog timer. Reset the watchdog timer after the watchdog timer interrupt is generated. For details, refer to 12. Watchdog Timer. 11.1.3.2 Oscillation Stop Detection Interrupt Oscillation Stop Detection Interrupt is generated by the oscillation stop detection function.
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R8C/14 Group, R8C/15 Group 11.1.5 11. Interrupt Interrupts and Interrupt Vector There are 4 bytes in one vector. Set the starting address of interrupt routine in each vector table. When an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector. Figure 11.2 shows the Interrupt Vector. MSB LSB Vector Address (L) Low Address Mid Address Vector Address (H) Figure 11.2 11.1.5.
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R8C/14 Group, R8C/15 Group 11.1.5.2 11. Interrupt Relocatable Vector Tables The relocatable vector tables occupy 256 bytes from the starting address set in the INTB register. Table 11.2 lists the Relocatable Vector Tables. Table 11.
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R8C/14 Group, R8C/15 Group 11.1.6 11. Interrupt Interrupt Control The following describes enable/disable the maskable interrupts and set the priority order to acknowledge. The contents explained does not apply to the nonmaskable interrupts. Use the I flag in the FLG register, IPL and the ILVL2 to ILVL0 bits in each interrupt control register to enable/disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control register. Figure 11.
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R8C/14 Group, R8C/15 Group 11.
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R8C/14 Group, R8C/15 Group 11.1.6.1 11. Interrupt I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts. 11.1.6.2 IR Bit The IR bit is set to “1” (interrupt requested) when an interrupt request is generated.
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R8C/14 Group, R8C/15 Group 11.1.6.4 11. Interrupt Interrupt Sequence An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine execution. When an interrupt request is generated while an instruction is executed, the CPU determines its interrupt priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle.
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R8C/14 Group, R8C/15 Group 11.1.6.5 11. Interrupt Interrupt Response Time Figure 11.6 shows an Interrupt Response Time. The interrupt response time is the period between an interrupt request generation and the execution of the first instruction in an interrupt routine. An interrupt response time includes the period between an interrupt request generation and the completed execution of an instruction (see #a in Figure 11.
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R8C/14 Group, R8C/15 Group 11.1.6.7 11. Interrupt Saving a Register In the interrupt sequence, the FLG register and PC are saved to the stack. After 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG register, extended to 16 bits, are saved to the stack, the 16 low-order bits in the PC are saved. Figure 11.7 shows the Stack State Before and After Acknowledgement of Interrupt Request.
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R8C/14 Group, R8C/15 Group 11.1.6.8 11. Interrupt Returning from an Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have been saved to the stack, are automatically returned. The program, executed before the interrupt request has been acknowledged, starts running again. Return the register saved by a program in an interrupt routine using the POPM instruction or others before the REIT instruction. 11.1.6.
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R8C/14 Group, R8C/15 Group 11. Interrupt 11.1.6.10 Interrupt Priority Judgement Circuit The interrupt priority judgement circuit selects the highest priority interrupt. Figure 11.10 shows the Judgement Circuit of Interrupts Priority Level.
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R8C/14 Group, R8C/15 Group 11.2 11. Interrupt INT Interrupt 11.2.1 INT0 Interrupt The INT0 interrupt is generated by an INT0 input. When using the INT0 interrupt, the INT0EN bit in the INTEN register is set to “1” (enable). The edge polarity is selected using the INT0PL bit in the INTEN register and the POL bit in the INT0IC register. Inputs can be passed through a digital filter with three different sampling clocks. The INT0 pin is shared with the external trigger input pin of timer Z. Figure 11.
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R8C/14 Group, R8C/15 Group 11.2.2 11. Interrupt INT0 Input Filter The INT0 input contains a digital filter. The sampling clock is selected by the INT0F1 to INT0F0 bits in the INT0F register. The IR bit in the INT0IC register is set to “1” (interrupt requested) when the INT0 level is sampled for every sampling clock and the sampled input level matches three times. Figure 11.12 shows the Configuration of INT0 Input Filter. Figure 11.13 shows the Operating Example of INT0 Input Filter.
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R8C/14 Group, R8C/15 Group 11.2.3 11. Interrupt INT1 Interrupt The INT1 interrupt is generated by INT1 inputs. The edge polarity is selected by the R0EDG bit in the TXMR register. When the CNTRSEL bit in the UCON register is set to “0”, the INT10 pin becomes the INT1 input pin. When the CNTRSEL bit is set to “1”, the INT11 pin becomes the INT1 input pin. The INT10 pin is shared with the CNTR00 pin and the INT11 pin is shared with the CNTR01 pin. Figure 11.
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R8C/14 Group, R8C/15 Group 11.2.4 11. Interrupt INT3 Interrupt The INT3 interrupt is generated by the INT3 input. Set the TCC07 bit in the TCC0 register to “0” (INT3). When the TCC06 bit in the TCC0 register is set to “0”, the INT3 interrupt request is generated synchronizing with the count source of timer C. When the TCC06 bit is set to “1”, the INT3 interrupt request is generated when the INT3 is input. The INT3 input contains a digital filter.
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R8C/14 Group, R8C/15 Group 11.
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R8C/14 Group, R8C/15 Group 11.3 11. Interrupt Key Input Interrupt A key input interrupt request is generated by one of the input edges of the K10 to K13 pins. The key input interrupt can be used as a key-on wake-up function to exit wait or stop mode. The KIiEN (i=0 to 3) bit in the KIEN register can select whether the pins are used as KIi input. The KIiPL bit in the KIEN register can select the input polarity.
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R8C/14 Group, R8C/15 Group 11.
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R8C/14 Group, R8C/15 Group 11.4 11. Interrupt Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the address indicated by the RMADi register (i=0, 1). This interrupt is used for a break function of the debugger. When using the on-chip debugger, do not set an address match interrupt (the registers of AIER, RMAD0, RMAD1 and the fixed vector tables) in a user system. Set the starting address of any instruction in the RMADi register.
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R8C/14 Group, R8C/15 Group 11. Interrupt Address Match Interrupt Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Bit Symbol AIER0 AIER1 — (b7-b2) Address 0009h Bit Name Address Match Interrupt 0 Enable Bit 0 : Disable 1 : Enable After Reset 00h Function RW RW Address Match Interrupt 1 Enable Bit 0 : Disable 1 : Enable RW Nothing is assigned. When w rite, set to “0”. When read, its content is “0”.
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R8C/14 Group, R8C/15 Group 12. Watchdog Timer 12. Watchdog Timer The watchdog timer is a function to detect when the program is out of control. To use the watchdog timer is recommend for improving reliability of a system. The watchdog timer contains a 15-bit counter and can select count source protection mode is enabled or disabled. Table 12.1 lists the Count Source Protection Mode is Enabled / Disabled Refer to 5.5 Watchdog Timer Reset for details of the watchdog timer reset. Figure 12.
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R8C/14 Group, R8C/15 Group 12.
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R8C/14 Group, R8C/15 Group 12. Watchdog Timer Watchdog Timer Reset Register b7 b0 Symbol WDTR Address 000Dh After Reset Indeterminate Function When w riting “00h” before w riting “FFh”, the w atchdog timer is reset.(1) The default value of the w atchdog timer is set to “7FFFh” w hen count source protection mode is disabled and “0FFFh” w hen count source protection mode is enabled.(2) RW WO NOTES : 1. Do not generate an interrupt betw een “00h” and the “FFh” w ritings. 2.
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R8C/14 Group, R8C/15 Group 12.1 12. Watchdog Timer When Count Source Protection Mode Disabled The count source of the watchdog timer is the CPU clock when count source protection mode is disabled. Table 12.2 lists the Specification of Watchdog Timer (When Count Source Protection Mode is Disabled). Table 12.
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R8C/14 Group, R8C/15 Group 12.2 12. Watchdog Timer When Count Source Protection Mode Enabled The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection mode is enabled. If the CPU clock stops when the program is out of control, the clock can be supplied to the watchdog timer. Table 12.3 lists the Specification of Watchdog Timer (When Count Source Protection Mode is Enabled). Table 12.
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R8C/14 Group, R8C/15 Group 13. Timers 13. Timers The microcomputer contains two 8-bit timers with 8-bit prescaler and a 16-bit timer. The two 8-bit timers with the 8-bit prescaler contain Timer X and Timer Z. These timers contain a reload register to memorize the default value of the counter. The 16-bit timer is Timer C which contains the input capture and output compare. All these timers operate independently.
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R8C/14 Group, R8C/15 Group 13.1 13. Timers Timer X Timer X is an 8-bit timer with an 8-bit prescaler. The prescaler and timer consist of the reload register and counter. The reload register and counter are allocated at the same address. When accessing the PREX and TX registers, the reload register and counter can be accessed (Refer to Tables 13.2 to 13.6 the Specification of Each Modes). Figure 13.1 shows the Block Diagram of Timer X. Figures 13.2 and 13.3 show the registers associated with Timer X.
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R8C/14 Group, R8C/15 Group 13.
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R8C/14 Group, R8C/15 Group 13.
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R8C/14 Group, R8C/15 Group 13.1.1 13. Timers Timer Mode Timer mode is mode to count the count source which is internally generated (See Table 13.2 Specification of Timer Mode). Figure 13.4 shows the TXMR Register in Timer Mode. Table 13.
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R8C/14 Group, R8C/15 Group 13.1.2 13. Timers Pulse Output Mode Pulse output mode is mode to count the count source internally generated and outputs the pulse which inverts the polarity from the CNTR0 pin each time the timer underflows (See Table 13.3 Specification of Pulse Output Mode). Figure 13.5 shows TXMR Register in Pulse Output Mode. Table 13.
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R8C/14 Group, R8C/15 Group 13.
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R8C/14 Group, R8C/15 Group 13.1.3 13. Timers Event Counter Mode Event counter mode is mode to count an external signal which inputs from the INT1/CNTR0 pin (See Table 13.4 Specification of Event Counter Mode). Figure 13.6 shows TXMR Register in Event Counter Mode. Table 13.
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R8C/14 Group, R8C/15 Group 13.
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R8C/14 Group, R8C/15 Group 13.1.4 13. Timers Pulse Width Measurement Mode Pulse width measurement mode is mode to measure the pulse width of an external signal which inputs from the INT1/CNTR0 pin (See Table 13.5 Specification of Pulse Width Measurement Mode). Figure 13.7 shows the TXMR Register in Pulse Width Measurement Mode. Figure 13.8 shows an Operating Example in Pulse Width Measurement Mode. Table 13.
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R8C/14 Group, R8C/15 Group 13.
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R8C/14 Group, R8C/15 Group 13.
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R8C/14 Group, R8C/15 Group 13.1.5 13. Timers Pulse Period Measurement Mode Pulse period measurement mode is mode to measure the pulse period of an external signal which inputs from the INT1/CNTR0 pin (See Table 13.6 Specification of Pulse Period Measurement Mode). Figure 13.9 shows the TXMR Register in Pulse Period Measurement Mode. Figure 13.10 shows an Operating Example in Pulse Period Measurement Mode. Table 13.
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R8C/14 Group, R8C/15 Group 13.
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R8C/14 Group, R8C/15 Group 13.
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R8C/14 Group, R8C/15 Group 13.2 13. Timers Timer Z Timer Z is an 8-bit timer with an 8-bit prescaler. The prescaler and timer consist of the reload register and counter. The reload register and counter are allocated at the same address. Refer to the Tables 13.7 to 13.12 for the Specification of Each Modes. Timer Z contains the timer Z primary and timer Z secondary as the reload register. Figure 13.11 shows the Block Diagram of Timer Z. Figures 13.12 to 13.
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R8C/14 Group, R8C/15 Group 13.
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R8C/14 Group, R8C/15 Group 13.
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R8C/14 Group, R8C/15 Group 13. Timers Timer Z Output Control Register(3) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol TZOC Bit Symbol Address 008Ah Bit Name Timer Z One-shot Start Bit(1) After Reset 00h Function 0 : One-shot stops 1 : One-shot starts Reserved Bit Set to “0” TZOCNT Timer Z Programmable Waveform Generation Output Sw itch Bit(2) 0 : Outputs programmable w aveform 1 : Outputs value in P1_3 port register — (b7-b3) Nothing is assigned. When w rite, set to “0”. When read, its content is “0”.
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R8C/14 Group, R8C/15 Group 13. Timers Timer Count Source Setting Register b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 Symbol TCSS Bit Symbol TXCK0 Address 008Eh Bit Name Timer X Count Source Select Bit(1) TZCK0 Reserved Bit Set to “0” Timer Z Count Source Select Bit(1) b5 b4 0 0 : f1 0 1 : f8 1 0 : Selects Timer X underflow 1 1 : f2 TZCK1 — (b7-b6) b1 b0 0 0 : f1 0 1 : f8 1 0 : fRING 1 1 : f2 TXCK1 — (b3-b2) After Reset 00h Function Reserved Bit Set to “0” NOTES : 1.
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R8C/14 Group, R8C/15 Group 13.2.1 13. Timers Timer Mode Timer mode is mode to count a count source which is internally generated or Timer X underflow (see Table 13.7 Specification of Timer Mode). The TZSC register is unused in timer mode. Figure 13.16 shows the TZMR and PUM Registers in Timer Mode. Table 13.
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R8C/14 Group, R8C/15 Group 13. Timers Timer Z Mode Register b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 Symbol Address 0080h TZMR Bit Symbol Bit Name — Reserved Bit (b3-b0) TZMOD0 TZMOD1 TZWC TZS After Reset 00h Function Set to “0” RW RW b5 b4 0 0 : Timer mode RW RW Timer Z Write Control Bit(1) 0 : Write to reload register and counter 1 : Write to reload register only RW Timer Z Count Start Flag(2) 0 : Stops counting 1 : Starts counting RW Timer Z Operating Mode Bit NOTES : 1.
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R8C/14 Group, R8C/15 Group 13.2.2 13. Timers Programmable Waveform Generation Mode Programmable waveform generation mode is mode to invert the signal output from the TZOUT pin each time the counter underflows, while the values in the TZPR and TZSC registers are counted alternately (See Table 13.8 Specification of Programmable Waveform Generation Mode). A counting starts by counting the value set in the TZPR register. Figure 13.17 shows TZMR and PUM Registers in Programmable Waveform Generation Mode.
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R8C/14 Group, R8C/15 Group 13. Timers Timer Z Mode Register b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 0 0 0 Symbol Address 0080h TZMR Bit Symbol Bit Name Reserved Bit — (b3-b0) TZMOD0 TZMOD1 Timer Z Operating Mode Bit Timer Z Write Control Bit TZWC TZS Timer Z Count Start Flag(2) After Reset 00h Function Set to “0” RW RW b5 b4 0 1 : Programmable Waveform Generation Mode RW RW Set to “1” in programmable w aveform generation mode(1) RW 0 : Stops counting 1 : Starts counting RW NOTES : 1.
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R8C/14 Group, R8C/15 Group 13.
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R8C/14 Group, R8C/15 Group 13.2.3 13. Timers Programmable One-shot Generation Mode Programmable one-shot generation mode is mode to output the one-shot pulse from the TZOUT pin by a program or an external trigger input (input to the INT0 pin). (see Table 13.9 Specification of Programmable One-Shot Generation Mode). When a trigger is generated, the timer starts operating from the point only once for a given period equal to the set value in the TZPR register. The TZSC register is unused in this mode.
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R8C/14 Group, R8C/15 Group 13. Timers Timer Z Mode Register b7 b6 b5 b4 b3 b2 b1 b0 1 1 0 0 0 0 0 Symbol Address 0080h TZMR Bit Symbol Bit Name — Reserved Bit (b3-b0) TZMOD0 TZMOD1 TZWC TZS Timer Z Operating Mode Bit After Reset 00h Function Set to “0” RW RW b5 b4 1 0 : Programmable one-shot generation mode RW RW Timer Z Write Control Bit Set to “1” in programmable one-shot generation mode(1) RW Timer Z Count Start Flag(2) 0 : Stops counting 1 : Starts counting RW NOTES : 1.
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R8C/14 Group, R8C/15 Group 13.
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R8C/14 Group, R8C/15 Group 13.2.4 13. Timers Programmable Wait One-shot Generation Mode Programmable wait one-shot generation mode is mode to output the one-shot pulse from the TZOUT pin by the external trigger input (input to the INT0 pin) (see Table 13.10 Specification of Programmable Wait One-Shot Generation Mode Specifications).
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R8C/14 Group, R8C/15 Group Table 13.10 13. Timers Specification of Programmable Wait One-Shot Generation Mode Specifications Item Count Source Count Operation Specification f1, f2, f8, Timer X underflow • Decrement the setting value in Timer Z primary • When a count of TZPR register underflows, the timer reloads the contents of the TZSC register before the count continues.
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R8C/14 Group, R8C/15 Group 13. Timers Timer Z Mode Register b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 0 0 0 0 Symbol Address 0080h TZMR Bit Symbol Bit Name — Reserved Bit (b3-b0) TZMOD0 Timer Z Operating Mode Bit After Reset 00h Function Set to “0” RW b5 b4 1 1 : Programmable w ait one-shot generation mode TZMOD1 TZWC TZS RW RW RW Timer Z Write Control Bit Set to “1” in programmable w ait one-shot generation mode(1) RW Timer Z Count Start Flag(2) 0 : Stops counting 1 : Starts counting RW NOTES : 1.
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R8C/14 Group, R8C/15 Group 13.
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R8C/14 Group, R8C/15 Group 13.3 13. Timers Timer C Timer C is a 16-bit timer. Figure 13.23 shows the Block Diagram of Timer C. Figure 13.24 shows the Block Diagram of CMP Waveform Generation Unit. Figure 13.25 shows the Block Diagram of CMP Waveform Output Unit. Timer C has two modes: input capture mode and output compare mode. Figure 13.26 to 13.29 show the Timer C-associated registers.
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R8C/14 Group, R8C/15 Group 13. Timers TCC14 TCC15 Compare 0 Interrupt Signal Compare 1 Interrupt Signal TCC16 TCC17 H L Reverse TCC17 to TCC16 T =11b D =10b =01b Latch Q R CMP Output (internal Signal) Reset Reverse L H TCC15 to TCC14 =01b =10b =11b TCC14 to TCC17: Bits in TCC1 register Figure 13.
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R8C/14 Group, R8C/15 Group 13. Timers Timer C Register (b15) b7 (b8) b0 b7 b0 Symbol TC Address 0091h-0090h After Reset 0000h RW Function Counts the internal count source. “0000h” can be read out by reading w hen the TCC00 bit is set to “0” (count stops). Count value can be read out by reading w hen the TCC00 bit is set to “1” (count starts).
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R8C/14 Group, R8C/15 Group 13.
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R8C/14 Group, R8C/15 Group 13.
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R8C/14 Group, R8C/15 Group 13.
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R8C/14 Group, R8C/15 Group 13.3.1 13. Timers Input Capture Mode Input capture mode is mode to input an edge to the TCIN pin or the fRING128 clock as trigger to latch the timer value and generates an interrupt request. The TCIN input contains a digital filter and this prevents an error caused by noise or so on from occurring. Table 13.11 shows Specification of Input Capture Mode. Figure 13.30 shows an Operating Example in Input Capture Mode. Table 13.
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R8C/14 Group, R8C/15 Group 13. Timers FFFFh Counter Contents (hex) Overflow Count Starts ←Measurement value 2 ← Measurement value 3 ←Measurement value 1 0000h Set to "0" by program Set to "1" by program TCC00 Bit in TCC0 Register Period “1” “0” The delay caused by digital filter and one count source cycle delay (max.
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R8C/14 Group, R8C/15 Group 13.3.2 13. Timers Output Compare Mode Output compare mode is mode to generate an interrupt request when the value of the TC register matches the value of the TM0 or TM1 register. Table 13.12 shows Specification of Output Compare Mode. Figure 13.31 shows an Operating Example in Output Compare Mode. Table 13.
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R8C/14 Group, R8C/15 Group 13.
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R8C/14 Group, R8C/15 Group 14. Serial Interface 14. Serial Interface Serial Interface is configured with one channels: UART0. UART0 has an exclusive timer to generate a transfer clock. Figure 14.1 shows a UART0 Block Diagram. Figure 14.2 shows a UART0 Transmit/Receive Unit. UART0 has two modes: clock synchronous serial I/O mode, and clock asynchronous serial I/O mode (UART mode). Figure 14.3 to 14.5 show the UART0-associated registers.
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R8C/14 Group, R8C/15 Group 14.
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R8C/14 Group, R8C/15 Group 14. Serial Interface UART0 Transmit Buffer Register(1, 2) (b15) b7 (b8) b0 b7 b0 Symbol U0TB Address 00A3h-00A2h After Reset Indeterminate RW Function — (b8-b0) Transmit data — (b15-b9) Nothing is assigned. When w rite, set to “0”. When read, its content is indeterminate. WO — NOTES : 1. When the transfer data length is 9-bit long, w rite to high-byte data first then low -byte data. 2. Use the MOV instruction to w rite to this register.
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R8C/14 Group, R8C/15 Group 14.
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R8C/14 Group, R8C/15 Group 14.
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R8C/14 Group, R8C/15 Group 14.1 14. Serial Interface Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode is mode to transmit and receive data using a transfer clock. Table 14.1 lists the Specification of Clock Synchronous Serial I/O Mode. Table 14.2 lists the Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode(1). Table 14.
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R8C/14 Group, R8C/15 Group Table 14.2 Register U0TB U0RB U0BRG U0MR U0C0 U0C1 UCON 14.
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R8C/14 Group, R8C/15 Group 14.
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R8C/14 Group, R8C/15 Group 14.1.1 14. Serial Interface Polarity Select Function Figure 14.7 shows the Transfer Clock Polarity. Use the CKPOL bit in the U0C0 register to select the transfer clock polarity.
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R8C/14 Group, R8C/15 Group 14.1.3 14. Serial Interface Continuous Receive Mode Continuous receive mode is held by setting the U0RRM bit in the UCON register to “1” (enables continuous receive mode). In this mode, reading U0RB register sets the TI bit in the U0C1 register to “0” (data in the U0TB register). When the U0RRM bit is set to “1”, do not write dummy data to the U0TB register in a program. Rev.2.
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R8C/14 Group, R8C/15 Group 14.2 14. Serial Interface Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmit and receive data after setting the desired bit rate and transfer data format. Table 14.4 lists the Specification of UART Mode. Table 14.5 lists the Registers to Be Used and Settings in UART Mode. Table 14.
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R8C/14 Group, R8C/15 Group Table 14.5 14.
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R8C/14 Group, R8C/15 Group 14.
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R8C/14 Group, R8C/15 Group 14.
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R8C/14 Group, R8C/15 Group 14.2.2 14. Serial Interface Bit Rate Divided-by-16 of frequency by the U0BRG register in UART mode is a bit rate. • When selecting internal clock Setting value to the U0BRG register = fj Bit Rate × 16 -1 Fj : Count source frequency of the U0BRG register (f1, f8 and f32) • When selecting external clock Setting value to the U0BRG register = fEXT Bit Rate × 16 -1 fEXT : Count source frequency of the U0BRG register (external clock) Figure 14.11 Table 14.
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R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU) 15. Clock Synchronous Serial I/O with Chip Select (SSU) The serial data of the clock synchronous can communicate for the clock synchronous serial I/O with chip select (hereinafter referred to as SSU). Table 15.1 shows a SSU Specification and Figure 15.1 shows a Block Diagram of SSU. Figure 15.2 to 15.8 show SSU Associated Registers. Table 15.
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R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU) f1 Internal Clock(f1/i) Internal Clock Generation Circuit Multiplexer SSCK SSMR Register SSCRL Register SSCRH Register Transmit / Receive Control Circuit SCS SSER Register SSMR2 Register SSTDR Register SSO Selector SSTRSR Register SSI SSRDR Register Interrupt Requests (TXI, TEI, RXI, OEI and CEI) i = 4, 8, 16, 32, 64, 128 and 256 Figure 15.1 Block Diagram of SSU Rev.2.
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R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU) SS Control Register H(4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol SSCRH Bit Symbol Address 00B8h Bit Name Transfer Clock Rate Select Bit(1) CKS1 CKS2 MSS Nothing is assigned. When w rite, set to “0”. When read, its content is “0”.
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R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU) SS Control Register L(4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address 00B9h SSCRL Bit Symbol Bit Name — Nothing is assigned. When w rite, set to “0”. (b0) When read, its content is “1”. SRES — (b3-b2) SOLP After Reset 01111101b Function RW — SSU Control Part Reset When this bit is set to “1”, the SSU control part and Bit SSTRSR register are reset. The values of the registers (1) in the SSU register are maintained.
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R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU) SS Mode Register (2) b7 b6 b5 b4 b3 b2 b1 b0 1 Symbol SSMR Bit Symbol Address 00BAh Bit Name Bit Counter 2 to 0 After Reset 00011000b Function 0 0 0 : 8-bit left 0 0 1 : 1-bit left 0 1 0 : 2-bit left 0 1 1 : 3-bit left 1 0 0 : 4-bit left 1 0 1 : 5-bit left 1 1 0 : 6-bit left 1 1 1 : 7-bit left BC0 BC1 BC2 — (b3) Reserved Bit — (b4) Nothing is assigned. When w rite, set to “0”. When read, its content is “1”.
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R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU) SS Enable Register(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol SSER Bit Symbol CEIE — (b2-b1) RE TE Address After Reset 00BBh 00h Bit Name Function Conflict Error Interrupt Enable Bit 0 : Disables conflict error interrupt request 1 : Enables conflict error interrupt request RW Nothing is assigned. When w rite, set to “0”. When read, its content is “0”.
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R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU) SS Status Register(7) b7 b6 b5 b4 b3 b2 b1 b0 Symbol SSSR Bit Symbol CE — (b1) Address 00BCh Bit Name Conflict Error Flag(1) Nothing is assigned. When w rite, set to “0”. When read, its content is “0”. (1) ORER — (b4-b3) RDRF After Reset 00h Function 0 : No conflict error occurs 1 : Conflict error occurs (2) Overrun Error Flag 0 : No overrun error occurs 1 : Overrun error occurs (3) Nothing is assigned.
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R8C/14 Group, R8C/15 Group 15.
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R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU) SS Transmit Data Register (2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol SSTDR Address 00BEh After Reset FFh Function Store the transmit data. The stored transmit data is transferred to the SSTRSR register and the transmit is started w hen detecting the SSTRSR register is empty. When the next transmit data is w ritten to the SSTDR register during the data transmit from the SSTRSR register, the data can be transmitted continuously.
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R8C/14 Group, R8C/15 Group 15.1 15. Clock Synchronous Serial I/O with Chip Select (SSU) Transfer Clock A transfer clock can be selected from 7 internal clocks (φ/256, φ/128, φ/64, φ/32, φ/16, φ/8 and φ/4) and an external clock. When using the SSU, set the SCKS bit in the SSMR2 register to “1” and select the SSCK pin as the serial clock pin. When the MSS bit in the SSCRH register is set to “1” (operates as master device), an internal clock can be selected and the SSCK pin functions as output.
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R8C/14 Group, R8C/15 Group 15.
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R8C/14 Group, R8C/15 Group 15.2 15. Clock Synchronous Serial I/O with Chip Select (SSU) SS Shift Register (SSTRSR) The SSTRSR register is the shift register to transmit and receive the serial data. When the transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the SSMR register is set to “0” (MSB-first), the bit 0 in the SSTDR register is transferred to the bit 0 in the SSTRSR register.
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R8C/14 Group, R8C/15 Group 15.3 15. Clock Synchronous Serial I/O with Chip Select (SSU) Interrupt Requests SSU has five interrupt requests : transmit data empty, transmit end, receive data full, overrun error and conflict error. Since these interrupt requests are assigned to the SSU interrupt vector table, determining interrupt sources by flags is required. Table 15.2 shows the SSU Interrupt Requests. Table 15.
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R8C/14 Group, R8C/15 Group 15.4 15. Clock Synchronous Serial I/O with Chip Select (SSU) Communication Modes and Pin Functions SSU switches functions of the I/O pin in each communication mode according to the setting of the MSS bit in the SSCRH register and the RE and TE bits in the SSER register. Table 15.3 shows the Association between Communication Modes and I/O Pins. Table 15.
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R8C/14 Group, R8C/15 Group 15.5 15. Clock Synchronous Serial I/O with Chip Select (SSU) Clock Synchronous Communication Mode 15.5.1 Initialization in Clock Synchronous Communication Mode Figure 15.11 shows an Initialization in Clock Synchronous Communication Mode. Set the TE bit in the SSER register to “0” (disables transmit) and the RE bit to “0” (disables receive) before data transmit / receive as an initialization.
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R8C/14 Group, R8C/15 Group 15.5.2 15. Clock Synchronous Serial I/O with Chip Select (SSU) Data Transmit Figure 15.12 shows an Example of SSU Operation for Data Transmit (Clock Synchronous Communication Mode). During the data transmit, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and data. When the SSU is set as a slave device, it outputs data synchronized with the input clock.
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R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU) Start Initialization (1) Read TDRE bit in SSSR register TDRE=1 ? No (1) After reading the SSSR register and confirming that the TDRE bit is set to “1”, write the transmit data to the SSTDR register. When write the transmit data to the SSTDR register, the TDRE bit is automatically set to “0”.
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R8C/14 Group, R8C/15 Group 15.5.3 15. Clock Synchronous Serial I/O with Chip Select (SSU) Data Receive Figure 15.14 shows an Example of Operation for Data Receive (Clock Synchronous Communication Mode). During the data receive, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the SSU is set as a salve device, it outputs data synchronized with the input clock.
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R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU) Start Initialization (1) Dummy read on SSRDR register (2) Last data received? Yes (1) After setting each register in the SSU register, dummy read on the SSRDR register is performed and receive operation is started. (2) Determine whether the last 1-byte data is received. When the last 1-byte data is received, set to stop after the data is received.
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R8C/14 Group, R8C/15 Group 15.5.4 15. Clock Synchronous Serial I/O with Chip Select (SSU) Data Transmit/Receive Data transmit/receive is a combined operation of data transmit and receive which are described before. Transmit/receive is started by writing data in the SSTDR register. When the 8th clock rises or the ORER bit is set to “1” (overrun error occurs) while the TDRE bit is set to “1” (data is transferred from the SSTDR to SSTRSR registers), the transmit/receive operation is stopped.
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R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU) Start Initialization (1) Read TDRE bit in SSSR register TDRE=1 ? No (1) After reading the SSSR register and confirming that the TDRE bit is set to “1”, write the transmit data in the SSTDR register. When writing the transmit data to the SSTDR register, the TDRE bit is automatically set to “0”.
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R8C/14 Group, R8C/15 Group 15.6 15. Clock Synchronous Serial I/O with Chip Select (SSU) Operation in 4-Wire Bus Communication Mode 4-wire bus communication mode is a mode which communicates with the 4-wire bus; a clock line, data input line, data output line and chip select line. This mode includes bidirectional mode in which the data input line and data output line function as a single pin.
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R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU) Start RE bit ← 0 TE bit ← 0 SSER register SSUMS bit ← 1 SSMR2 register (1) SSMR register Set CPHS and CPOS bits MLS bits ← 0 SSCRH register (2) SSCRH register (2) Set the BIDE bit to “1” in bidirectional mode and the I/O of the #SCS pin is set by the CSSO to CSS1 bits.
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R8C/14 Group, R8C/15 Group 15.6.2 15. Clock Synchronous Serial I/O with Chip Select (SSU) Data Transmit Figure 15.18 shows an Example of Operation in Data Transmit (4-Wire Bus Communication Mode). During the data transmit, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and data. When the UUSA is set as a slave device, it outputs data in synchronized with the input clock while “L” applies to the SCS pin.
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R8C/14 Group, R8C/15 Group 15.
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R8C/14 Group, R8C/15 Group 15.6.3 15. Clock Synchronous Serial I/O with Chip Select (SSU) Data Receive Figure 15.19 shows an example of the SSU operation for the data receive. During the data receive, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the SSU is set as a salve device, it outputs data synchronized with the input clock while the SCS pin is held “L” input.
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R8C/14 Group, R8C/15 Group 15.
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R8C/14 Group, R8C/15 Group 15.6.4 15. Clock Synchronous Serial I/O with Chip Select (SSU) SCS Pin Control and Arbitration When setting the SSUMS bit in the SSMR2 register to “1” (4-wire bus communication mode).and the CSS1 bit in the SSMR2 register to “1” (functions as SCS output pin), Set the MSS bit in the SSCRH register to “1” (operates as a master device) and check the arbitration of the SCS pin before starting serial transfer.
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R8C/14 Group, R8C/15 Group 16. A/D Converter 16. A/D Converter The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling amplifier. The analog input shares the pins with P1_0 to P1_3. Therefore, when using these pins, ensure the corresponding port direction bits are set to “0” (input mode).
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R8C/14 Group, R8C/15 Group 16.
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R8C/14 Group, R8C/15 Group 16.
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R8C/14 Group, R8C/15 Group 16. A/D Converter A/D Control Register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 Symbol ADCON2 Bit Symbol Address 00D4h Bit Name A/D Conversion Method Select Bit After Reset 00h Function 0 : Without sample and hold 1 : With sample and hold — (b3-b1) Reserved Bit Set to “0” — (b7-b4) Nothing is assigned. When w rite, set to “0”. When read, its content is “0”. SMP RW RW RW — NOTES : 1.
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R8C/14 Group, R8C/15 Group 16.1 16. A/D Converter One-Shot Mode In one-shot mode, the input voltage on one selected pin is A/D converted once. Table 16.2 lists the Specification of One-Shot Mode. Figure 16.4 shows the ADCON0 and ADCON1 Registers in One-Shot Mode. Table 16.2 Specification of One-Shot Mode Item Function Start Condition Stop Condition Interrupt Request Generation Timing Input Pin Reading of A/D Conversion Result Rev.2.
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R8C/14 Group, R8C/15 Group 16.
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R8C/14 Group, R8C/15 Group 16.2 16. A/D Converter Repeat Mode In repeat mode, the input voltage on one selected pin is A/D converted repeatedly. Table 16.3 lists the Repeat Mode Specifications. Figure 16.5 shows the ADCON0 and ADCON1 Registers in Repeat Mode. Table 16.
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R8C/14 Group, R8C/15 Group 16.
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R8C/14 Group, R8C/15 Group 16.3 16. A/D Converter Sample and Hold When the SMP bit in the ADCON2 register is set to “1” (with sample and hold function), A/D conversion rate per pin increases to 28φAD cycles for 8-bit resolution or 33φAD cycles for 10-bit resolution. The sample and hold function is available in all operating modes. Start the A/D conversion after selecting whether the sample and hold circuit is to be used or not.
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R8C/14 Group, R8C/15 Group 16.5 16. A/D Converter Internal Equivalent Circuit of Analog Input Figure 16.8 shows the Internal Equivalent Circuit of Analog Input. VCC VCC VSS AVCC ON Resistor Approx. 2kΩ Wiring Resistor Approx. 0.2kΩ Parasitic Diode AN8 SW1 ON Resistor Approx. 0.6kΩ Analog Input Voltage SW2 Parasitic Diode i Ladder-type Switches i=4 AMP VIN ON Resistor Approx. 5kΩ Sampling Control Signal VSS C = Approx.1.5pF SW3 SW4 i Ladder-type Wiring Resistors AVSS ON Resistor Approx.
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R8C/14 Group, R8C/15 Group 16.6 16. A/D Converter Inflow Current Bypass Circuit Figure 16.9 shows the Configuration of the Inflow Current Bypass Circuit, Figure 16.10 shows the Example of an Inflow Current Bypass Circuit where VCC or More is Applied. OFF OFF Fixed to GND level Unselected Channel ON To the internal logic of the A/D Converter ON External input latched into Selected Channel ON OFF Figure 16.
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R8C/14 Group, R8C/15 Group 17. Programmable I/O Ports 17. Programmable I/O Ports Programmable Input/Output ports (hereafter referred to as “I/O ports”) have 13 ports of the P1, P3_3 to P3_5, P3_7, and P4_5. Also, the main clock oscillation circuit is not used, the P4_6 and P4_7 can be used as the input port only. Table 17.1 lists the Overview of Programmable I/O Ports. Table 17.
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R8C/14 Group, R8C/15 Group 17. Programmable I/O Ports P1_0 to P1_3 Pull-up Selection Direction Register "1" Output from each peripheral function Data Bus Port Latch (Note 1) Drive Capacity Selection Input to each peripheral function Analog Input P1_4 Pull-Up Selection Direction Register “1” Output from each peripheral function Data Bus Port Latch (Note 1) P1_5 Pull-Up Selection Direction Register Data Bus Port Latch (Note 1) Input to each peripheral function NOTES : 1.
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R8C/14 Group, R8C/15 Group 17.
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R8C/14 Group, R8C/15 Group 17. Programmable I/O Ports P4_5 Pull-Up Selection Direction Register Data Bus Port Latch (Note 4) Input to each peripheral function Digital Filter P4_6/XIN Data Bus (Note 4) Clocked Inverter(1) (Note 2) P4_7/XOUT (Note 3) Data Bus (Note 4) NOTES: 1. When CM05=1, CM10=1, or CM13=0, the clocked inverter is cutoff. 2. When CM10=1 or CM13=0, the feedback resistor is unconnected. 3. When CM05=CM13=1 or CM10=CM13=1, this pin is pulled up. 4. symbolizes a parasitic diode.
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R8C/14 Group, R8C/15 Group 17. Programmable I/O Ports MODE MODE Signal Input (Note 1) RESET RESET Signal Input (Note 1) NOTES : 1. symbolizes a parasitic diode. Ensure the input voltage on each port will not exceed VCC. Figure 17.4 Configuration of I/O Pins Rev.2.
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R8C/14 Group, R8C/15 Group 17.
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R8C/14 Group, R8C/15 Group 17. Programmable I/O Ports Pull-Up Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol PUR0 Bit Symbol (b1-b0) PU02 PU03 — (b5-b4) PU06 PU07 A ddress 00FCh Bit Name A f ter Reset 00XX0000b Function Set to “0” Reserved Bit 0 : Not pulled up P1_0 to P1_3 pull-up(1) 1 : Pulled up P1_4 to P1_7 pull-up(1) Nothing is assigned. When w rite, set to “0”. When read, its content is indeterminate.
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R8C/14 Group, R8C/15 Group 17.4 17. Programmable I/O Ports Port setting Table 17.4 to Table 17.17 list the port setting. Table 17.
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R8C/14 Group, R8C/15 Group Table 17.7 17.
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R8C/14 Group, R8C/15 Group Table 17.10 17. Programmable I/O Ports Port P1_6/CLK0/SSI Setting Register PD1 PUR0 U0MR Bit PD1_6 PU03 SMD2, SMD1, SMD0, CKDIR 0 0 Other than 0X10b 0 1 Other than 0X10b 0 0 XXX1b 1 X Other than 0X10b X X 0X10b Setting Value Function Input port (not pulled up) Input port (pulled up) CLK0 (external clock) input Output port CLK0 (internal clock) output X: “0” or “1” Table 17.
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R8C/14 Group, R8C/15 Group Table 17.14 17. Programmable I/O Ports Port P3_5/SSCK/CMP1_2 Setting SSU (Refer to Table 15.
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R8C/14 Group, R8C/15 Group 17.5 17. Programmable I/O Ports Unassigned Pin Handling Table 17.18 lists the Unassigned Pin Handling. Figure 17.9 show the Unassigned Pin Handling. Table 17.18 Unassigned Pin Handling Pin Name Ports P1, P3_3 to P3_5, P3_7, P4_5 Connection • After setting to input mode, connect every pin to VSS via a resistor (pulldown) or connect every pin to VCC via a resistor (pull-up).(2) • After setting to output mode, leave these pins open.
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R8C/14 Group, R8C/15 Group 18. Flash Memory Version 18. Flash Memory Version 18.1 Overview In the flash memory version, rewrite operations to the flash memory can be performed in three modes; CPU rewrite, standard serial I/O, parallel I/O modes. Table 18.1 lists the Flash Memory Version Performance (see Table 1.1 Performance Outline of the R8C/ 14 Group and Table 1.2 Performance Outline of the R8C/15 Group for the items not listed on Table 18.1). Table 18.
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R8C/14 Group, R8C/15 Group Table 18.2 18. Flash Memory Version Flash Memory Rewrite Modes Flash Memory Rewrite mode Function CPU Rewrite Mode User ROM area is rewritten by executing software commands from the CPU. EW0 mode: Rewritable in any area other than flash memory EW1 mode: Rewritable in flash memory Areas which can User ROM area be rewritten Operating Mode Single chip mode ROM None Programmer Rev.2.
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R8C/14 Group, R8C/15 Group 18.2 18. Flash Memory Version Memory Map The flash memory contains a user ROM area and a boot ROM area (reserved area). Figure 18.1 shows the Flash Memory Block Diagram for R8C/14 Group. Figure 18.2 shows the Flash Memory Block Diagram for R8C/15 Group. The user ROM area of R8C/15 group contains an area (program ROM) which stores a microcomputer operating program and the 1-Kbyte Block A and B (data flash). The user ROM area is divided into several blocks.
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R8C/14 Group, R8C/15 Group 18.
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R8C/14 Group, R8C/15 Group 18.3 18. Flash Memory Version Functions To Prevent Flash Memory from Rewriting Standard serial I/O mode contains an ID code check function, and the parallel I/O mode contains a ROM code protect function to prevent the flash memory from reading or rewriting easily. 18.3.1 ID Code Check Function Use this function in standard serial I/O mode.
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R8C/14 Group, R8C/15 Group 18.3.2 18. Flash Memory Version ROM Code Protect Function The ROM code protect function disables to read and change the internal flash memory by the OFS register in parallel I/O mode. Figure 18.4 shows the OFS Register. The ROM code protect function is enabled by writing “0” to the ROMCP1 bit and “1” to the ROMCR bit and disables to read and change the internal flash memory.
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R8C/14 Group, R8C/15 Group 18.4 18. Flash Memory Version CPU Rewrite Mode In CPU rewrite mode, user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on a board without using such as a ROM programmer. Execute the program and block erase commands only to each block in user ROM area.
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R8C/14 Group, R8C/15 Group 18.4.1 18. Flash Memory Version EW0 Mode The microcomputer enters CPU rewrite mode and software commands can be acknowledged by setting the FMR01 bit in the FMR0 register to “1” (CPU rewrite mode enabled). In this case, since the FMR11 bit in the FMR1 register is set to “0”, EW0 mode is selected. Use software commands to control a program and erase operations. The FMR0 register or the status register can determine status when program and erase operation complete.
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R8C/14 Group, R8C/15 Group 18. Flash Memory Version Figure 18.5 shows the FMR0 Register. Figure 18.6 shows the FMR1 and FMR4 Registers. 18.4.2.1 FMR00 Bit This bit indicates the operating status of the flash memory. The bit is “0” during programming, erasing, or erase-suspend mode; otherwise, the bit is “1”. 18.4.2.2 FMR01 Bit The microcomputer is made ready to accept commands by setting the FMR01 bit to “1” (CPU rewrite mode). 18.4.2.
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R8C/14 Group, R8C/15 Group 18. Flash Memory Version 18.4.2.10 FMR40 bit The erase-suspend function is enabled by setting the FMR40 bit to “1” (enable). 18.4.2.11 FMR41 bit In EW0 mode, the microcomputer enters erase-suspend mode when setting the FMR41 bit to “1” by a program. The FMR41 bit is automatically set to “1” (requests erase-suspend) when an interrupt request of an enabled interrupt is generated in EW1 mode, and then the microcomputer enters erasesuspend mode.
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R8C/14 Group, R8C/15 Group 18. Flash Memory Version Flash Memory Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 0 Symbol Address 01B5h FMR1 Bit Symbol Bit Name — Reserved Bit (b0) FMR11 — (b4-b2) FMR15 FMR16 — (b7) After Reset 1000000Xb Function When read, its content is indeterminate.
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R8C/14 Group, R8C/15 Group 18. Flash Memory Version Figure 18.7 shows the Timing on Suspend Operation. Erase Starts Erase Suspends During Erase FMR00 Bit in FMR0 Register “1” “0” FMR46 Bit in FMR4 Register “1” “0” Check that the FMR00 bit is set to “0”, and that the erase operation has not ended. Figure 18.7 Timing on Suspend Operation Rev.2.10 Jan 19, 2006 REJ09B0164-0210 Page 202 of 253 Erase Restarts Erase Ends During Erase Check the Status, and that the erase operation ends normally.
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R8C/14 Group, R8C/15 Group 18. Flash Memory Version Figure 18.8 shows the How to Set and Exit EW0 Mode. Figure 18.9 shows the How to Set and Exit EW1 Mode.
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R8C/14 Group, R8C/15 Group 18. Flash Memory Version On-Chip Oscillator Mode (Main Clock Stops) Program Transfer a on-chip oscillator mode (main clock stops) program to any areas other the flash memory Jump to the on-chip oscillator mode (main clock stops) program which has been transferred to any areas other the flash memory. (The subsequent processing is executed by a program in any areas other than the flash memory.
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R8C/14 Group, R8C/15 Group 18.4.3 18. Flash Memory Version Software Commands Software commands are described below. Read or write commands and data from or to in 8-bit units. Table 18.
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R8C/14 Group, R8C/15 Group 18.4.3.4 18. Flash Memory Version Program Command The program command writes data to the flash memory in 1-byte units. Write “40h” in the first bus cycle and write data to the write address in the second bus cycle, and an auto program operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the same address as the write address specified in the second bus cycle.
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R8C/14 Group, R8C/15 Group 18.4.3.5 18. Flash Memory Version Block Erase If writing ”20h” in the first bus cycle and “D0h” to the given address of a block in the second bus cycle, and an auto erase operation (erase and verify) will start. The FMR00 bit in the FMR0 register can determine whether auto erasing has completed. The FMR00 bit is set to “0” during auto erasing and set to “1” when auto erasing completes.
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R8C/14 Group, R8C/15 Group 18.
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R8C/14 Group, R8C/15 Group 18.4.4 18. Flash Memory Version Status Register The status register indicates the operating status of the flash memory and whether an erasing or programming operation completes normally or in error. Status of the status register can be read by the FMR00, FMR06, and FMR07 bits in the FMR0 register. Table 18.5 lists the Status Register.
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R8C/14 Group, R8C/15 Group 18.4.5 18. Flash Memory Version Full Status Check When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating occurrence of each specific error. Therefore, Checking these status bits (full status check) can determine the executed result. Table 18.6 lists the Errors and FMR0 Register Status. Figure 18.14 shows the Full Status Check and Handling Procedure for Each Error. Table 18.
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R8C/14 Group, R8C/15 Group 18.
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R8C/14 Group, R8C/15 Group 18.5 18. Flash Memory Version Standard Serial I/O Mode In standard serial I/O mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by using a serial programmer which is applicable for this microcomputer. Standard serial I/O mode is used to connect with a serial writer using a special clock asynchronous serial I/O. There are three types of Standard serial I/O modes: • Standard serial I/O mode 1 ..........
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R8C/14 Group, R8C/15 Group Table 18.8 18. Flash Memory Version Pin Functions (Flash Memory Standard Serial I/O Mode 3) Pin VCC,VSS Name Power input I/O RESET P4_6/XIN Reset input I P4_6 input/clock input I P4_7/XOUT P4_7 input/clock output AVCC, AVSS VREF P1_0 to P1_7 P3_3 to P3_5, P3_7 P4_5 MODE Analog power supply input Reference voltage input Input port P1 Input port P3 I I I I Input port P4 MODE I Input “H” or “L” level signal or leave the pin open. I/O Serial data I/O pin.
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R8C/14 Group, R8C/15 Group 18. Flash Memory Version 20 2 19 3 18 R8C/14, R8C/15 Group RESET 1 4 Connect Oscillator Circuit(1) VSS 5 6 7 8 MODE 17 16 VCC 15 14 13 9 12 10 11 Package: PLSP0020JB-A NOTES: 1. No need to connect an oscillating circuit when operating with on-chip oscillator clock. Mode Setting Figure 18.15 Signal Value MODE Voltage from programmer RESET VSS → VCC Pin Connections for Standard Serial I/O Mode 3 Rev.2.
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R8C/14 Group, R8C/15 Group 18.5.1.1 18. Flash Memory Version Example of Circuit Application in the Standard Serial I/O Mode Figure 18.16 show Pin Process in Standard Serial I/O Mode 2, Figure 18.17 show Pin Process in Standard Serial I/O Mode 3. Since the controlled pins vary depending on the programmer, refer to the manual of your serial programmer. Microcomputer Data Output TXD Data Input RXD MODE NOTES: 1.
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R8C/14 Group, R8C/15 Group 18.6 18. Flash Memory Version Parallel I/O Mode Parallel I/O mode is used to input and output the required software command, address and data parallel to controls (read, program and erase) for internal flash memory. Use a parallel programmer which supports this microcomputer. Contact the manufacturer of your parallel programmer about the parallel programmer and refer to the user’s manual of your parallel programmer for details on how to use it.
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R8C/14 Group, R8C/15 Group 19. Electrical Characteristics 19. Electrical Characteristics Table 19.1 Absolute Maximum Ratings Symbol VCC AVCC Parameter Supply Voltage Analog Supply Voltage VI VO Pd Topr Tstg Input Voltage Output Voltage Power Dissipation Operating Ambient Temperature Storage Temperature Table 19.
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R8C/14 Group, R8C/15 Group Table 19.3 A/D Converter Characteristics Symbol − − 19. Electrical Characteristics Parameter Resolution Absolute Accuracy Conditions Vref = VCC φAD = 10MHz, Vref = VCC = 5.0V φAD = 10MHz, Vref = VCC = 5.0V 10-Bit Mode 8-Bit Mode 10-Bit Mode φAD = 10MHz, Vref = VCC = 3.3V(3) Resistor Ladder Conversion Time 10-Bit Mode 8-Bit Mode Vref Reference voltage VIA − Analog Input Voltage A/D Operating Without Sample & Hold Clock With Sample & Hold Frequency(2) Standard Typ.
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R8C/14 Group, R8C/15 Group Table 19.4 Flash Memory (Program ROM) Electrical Characteristics Symbol − − 19. Electrical Characteristics Parameter Program/Erase Endurance(2) Conditions R8C/14 Group 100(3) R8C/15 Group 1,000(3) − − − VCC = 5.0 V at Topr = 25 °C VCC = 5.
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R8C/14 Group, R8C/15 Group Table 19.5 Flash Memory (Data flash Block A, Block B) Electrical Characteristics Symbol − − − − − td(SR-ES) − − − − − 19.
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R8C/14 Group, R8C/15 Group 19. Electrical Characteristics Erase-Suspend Request (Maskable interrupt Request) FMR46 td(SR-ES) Figure 19.2 Table 19.
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R8C/14 Group, R8C/15 Group Table 19.8 19. Electrical Characteristics Reset Circuit Electrical Characteristics (When Using Voltage Monitor 1 Reset ) Symbol Parameter Condition Standard Typ. Max. − Vdet1 − 100 Min. − − Power-On Reset Valid Voltage -20°C ≤ Topr < 85°C Vpor2 tw(Vpor2-Vdet1) Supply Voltage Rising Time When Power-On Reset is -20°C ≤ Topr < 85°C, Deasserted(1) tw(por2) ≥ 0s(3) Unit V ms NOTES: 1. This condition is not applicable when using with Vcc ≥ 1.0V. 2.
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R8C/14 Group, R8C/15 Group Table 19.10 19. Electrical Characteristics High-speed On-Chip Oscillator Circuit Electrical Characteristics Symbol Parameter − Condition High-Speed On-Chip Oscillator Frequency VCC = 5.0V, Topr = 25 °C When the Reset is Deasserted High-Speed On-Chip Oscillator Frequency 0 to +60 °C / 5 V ± 5 %(2) Temperature • Supplay Voltage Dependence −20 to +85 °C / 2.7 to 5.5 V(2) − −40 to +85 °C / 2.7 to 5.5 V(2) Min. − Standard Typ. 8 7.44 − 7.04 6.80 Unit Max. − MHz − 8.
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R8C/14 Group, R8C/15 Group 19.
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R8C/14 Group, R8C/15 Group 19.
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R8C/14 Group, R8C/15 Group 19. Electrical Characteristics tHI VIH or VOH SSCK VIH or VOH tLO tSUCYC SSO(Output) tOD SSI(Input) tSU Figure 19.6 tH I/O Timing of Clock Synchronous Serial I/O (SSU) with Chip Select (Clock Synchronous Communication Mode) Rev.2.
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R8C/14 Group, R8C/15 Group Table 19.13 Electrical Characteristics (1) [VCC = 5V] Symbol VOH 19. Electrical Characteristics IOH = -1mA Standard Min. Typ. VCC − 2.0 − VCC − 0.3 − VCC − 2.0 − Max. VCC VCC VCC IOH = -500µA VCC − 2.0 − VCC V − − − − IOL = 15mA − − 2.0 0.45 2.0 V V V IOL = 5mA − − 2.0 V IOL = 200µA − − 0.45 V IOL = 1mA − − 2.0 V IOL = 500µA − − 2.0 V INT0, INT1, INT3, KI0, KI1, KI2, KI3, CNTR0, CNTR1, TCIN, RXD0, SSO 0.2 − 1.0 V RESET 0.2 − 2.
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R8C/14 Group, R8C/15 Group Table 19.14 Symbol ICC 19. Electrical Characteristics Electrical Characteristics (2) [Vcc = 5V] (Topr = -40 to 85 °C, unless otherwise specified.) Parameter Condition Power Supply Current (VCC=3.3 to 5.5V) In single-chip mode, the output pins are open and other pins are VSS High-Speed Mode MediumSpeed Mode High-Speed On-Chip Oscillator Mode Low-Speed On-Chip Oscillator Mode Wait Mode Wait Mode Stop Mode Rev.2.
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R8C/14 Group, R8C/15 Group 19. Electrical Characteristics Timing Requirements (Unless otherwise specified: VCC = 5V, VSS = 0V at Topr = 25 °C) [ VCC = 5V ] Table 19.15 XIN Input Symbol tc(XIN) tWH(XIN) tWL(XIN) Table 19.16 Parameter XIN Input Cycle Time XIN Input “H” Width XIN Input “L” Width Table 19.17 Unit ns ns ns CNTR0 Input, CNTR1 Input, INT1 Input Symbol tc(CNTR0) tWH(CNTR0) tWL(CNTR0) Standard Min. Max.
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R8C/14 Group, R8C/15 Group 19. Electrical Characteristics VCC = 5V tc(CNTR0) tWH(CNTR0) CNTR0 Input tWL(CNTR0) tc(TCIN) tWH(TCIN) TCIN Input tWL(TCIN) tc(XIN) tWH(XIN) XIN Input tWL(XIN) tc(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TxDi td(C-Q) tsu(D-C) RxDi tW(INL) INTi Input Figure 19.7 tW(INH) Timing Diagram When VCC = 5V Rev.2.
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R8C/14 Group, R8C/15 Group Table 19.20 Electrical Characteristics (3) [VCC = 3V] Symbol VOH VOL Parameter Output “H” Voltage Except XOUT XOUT Output “L” Voltage Except P1_0 to P1_3, XOUT P1_0 to P1_3 XOUT VT+-VT- IIH IIL RPULLUP RfXIN fRING-S VRAM 19.
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R8C/14 Group, R8C/15 Group Table 19.21 Symbol ICC 19. Electrical Characteristics Electrical Characteristics (4) [Vcc = 3V] (Topr = -40 to 85 °C, unless otherwise specified.) Parameter Condition Power Supply Current (VCC=2.7 to 3.3V) In single-chip mode, the output pins are open and other pins are VSS High-Speed Mode MediumSpeed Mode High-Speed On-Chip Oscillator Mode Low-Speed On-Chip Oscillator Mode Wait Mode Wait Mode Stop Mode Rev.2.
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R8C/14 Group, R8C/15 Group 19. Electrical Characteristics Timing requirements (Unless otherwise specified: VCC = 3V, VSS = 0V at Topr = 25 °C) [VCC = 3V] Table 19.22 XIN Input Symbol tc(XIN) tWH(XIN) tWL(XIN) Table 19.23 Parameter XIN Input Cycle Time XIN Input “H” Width XIN Input “L” Width Table 19.24 Unit ns ns ns CNTR0 Input, CNTR1 Input, INT1 Input Symbol tc(CNTR0) tWH(CNTR0) tWL(CNTR0) Standard Min. Max.
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R8C/14 Group, R8C/15 Group 19. Electrical Characteristics VCC = 3V tc(CNTR0) tWH(CNTR0) CNTR0 Input tWL(CNTR0) tc(TCIN) tWH(TCIN) TCIN Input tWL(TCIN) tc(XIN) tWH(XIN) XIN Input tWL(XIN) tc(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TxDi td(C-Q) tsu(D-C) RxDi tW(INL) INTi Input Figure 19.8 tW(INH) Timing Diagram When VCC = 3V Rev.2.
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R8C/14 Group, R8C/15 Group 20. Precautions 20. Precautions 20.1 Stop Mode and Wait Mode 20.1.1 Stop Mode When entering stop mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) and the CM10 bit to “1” (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit in the CM1 register to “1” (stop mode) and the program stops. Insert at least 4 NOP instructions after inserting the JMP.B instruction immediately after the instruction which sets the CM10 bit to “1”.
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R8C/14 Group, R8C/15 Group 20.2 20. Precautions Interrupts 20.2.1 Reading Address 00000h Do not read the address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At this time, the acknowledged interrupt IR bit is set to “0”.
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R8C/14 Group, R8C/15 Group 20.2.5 20. Precautions Changing Interrupt Factor The IR bit in the interrupt control register may be set to “1” (interrupt requested) when the interrupt factor changes. When using an interrupt, set the IR bit to “0” (no interrupt requested) after changing the interrupt factor. In addition, the changes of interrupt factors include all factors that change the interrupt factors assigned to individual software interrupt numbers, polarities, and timing.
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R8C/14 Group, R8C/15 Group 20.2.6 20. Precautions Changing Interrupt Control Register (a) Each interrupt control register can only be changed while interrupt requests corresponding to that register are not generated. If interrupt requests may be generated, disable the interrupts before changing the interrupt control register. (b) When changing any interrupt control register after disabling interrupts, be careful with the instructions to be used.
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R8C/14 Group, R8C/15 Group 20.3 20. Precautions Clock Generation Circuit 20.3.1 Oscillation Stop Detection Function Since the oscillation stop detection function cannot be used if the main clock frequency is below 2MHz, set the OCD1 to OCD0 bits to “00b” (oscillation stop detection function disabled). 20.3.2 Oscillation Circuit Constants Ask the maker of the oscillator to specify the best oscillation circuit constants on your system. Rev.2.
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R8C/14 Group, R8C/15 Group 20.4 20. Precautions Timers 20.4.1 Timers X and Z • Timers X and Z stop counting after reset. Set the value to these timers and prescalers before the count starts. • Even if the prescalers and timers are read out in 16-bit units, these registers are read by 1 byte in the microcomputer. Consequently, the timer value may be updated during the period these two registers are being read. 20.4.
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R8C/14 Group, R8C/15 Group 20.4.3 20. Precautions Timer Z • Do not rewrite the TZMOD0 to TZMOD1 bits and the TZS bit simultaneously. • In programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the TZS bit in the TZMR register to “0” (stops counting) or setting the TZOS bit in the TZOC register to “0” (stops one-shot), the timer reloads the value of reload register and stops.
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R8C/14 Group, R8C/15 Group 20.5 20. Precautions Serial Interface • When reading data from the U0RB (i = 0, 1) register even in the clock asynchronous serial I/O mode or in the clock synchronous serial I/O mode. Ensure to read data in 16-bit unit. When the high-order byte of the U0RB register is read, the PER and FER bits in the U0RB register and the RI bit in the U0C1 register are set to “0”. Example (when reading receive buffer register): MOV.
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R8C/14 Group, R8C/15 Group 20.6 20. Precautions Clock Synchronous Serial I/O (SSU) with Chip Select 20.6.1 Access Registers Associated with SSU After the conditions of “3 instructions or more after writing to the registers associated with SSU (00B8h to 00BFh)“ or “4 cycles or more after writing to them” are met, read those registers. • An example to wait for 3 instructions or more Program Example MOV.B NOP NOP NOP MOV.B • An example to wait for 4 cycles or more Program Example BCLR JMP.
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R8C/14 Group, R8C/15 Group 20.7 20. Precautions A/D Converter • Write to each bit (other than bit 6) in the ADCON0 register, each bit in the ADCON1 register, or the • • • • • SMP bit in the ADCON2 register when the A/D conversion stops (before a trigger occurs). When the VCUT bit in the ADCON1 register is changed from “0” (VREF not connected) to “1” (VREF connected), wait for at least 1µs or longer before the A/D conversion starts. When changing A/D operating mode, select an analog input pin again.
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R8C/14 Group, R8C/15 Group 20.8 20. Precautions Flash Memory Version 20.8.1 CPU Rewrite Mode 20.8.1.1 Operating Speed Before entering CPU rewrite mode (EW0 mode), select 5MHz or below for the CPU clock using the CM06 bit in the CM0 register and the CM16 to CM17 bits in the CM1 register. This usage note is not needed for EW1 mode. 20.8.1.
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R8C/14 Group, R8C/15 Group Table 20.2 Mod e 20.
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R8C/14 Group, R8C/15 Group 20.8.1.4 20. Precautions How to Access Write “0” to the corresponding bits before writing “1” when setting the FMR01, FMR02, or FMR11 bit to “1”. Do not generate an interrupt between writing “0” and “1”. 20.8.1.5 Rewriting User ROM Area In EW0 Mode, if the power supply voltage drops while rewriting any block in which the rewrite control program is stored, the flash memory may not be able to be rewritten because the rewrite control program cannot be rewritten correctly.
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R8C/14 Group, R8C/15 Group 20.9 20. Precautions Noise 20.9.1 Insert a bypass capacitor between VCC and VSS pins as the countermeasures against noise and latch-up Connect the bypass capacitor (at least 0.1µF) using the shortest and thickest as possible. 20.9.2 Countermeasures against Noise Error of Port Control Registers During severe noise testing, mainly power supply system noise, and introduction of external noise, the data of port related registers may be changed.
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R8C/14 Group, R8C/15 Group 21. Precaution for On-chip Debugger 21. Precaution for On-chip Debugger When using the on-chip debugger to develop the R8C/14 and R8C/15 groups program and debug, pay the following attention. (1) (2) (3) (4) Do not use from OC000h address to OC7FFh because the on-chip debugger uses these addresses. Do not set the address match interrupt (the registers of AIER, RMAD0, RMAD1 and the fixed vector tables) in a user system. Do not use the BRK instruction in a user system.
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R8C/14 Group, R8C/15 Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code P-LSSOP20-4.4x6.5-0.65 RENESAS Code PLSP0020JB-A MASS[Typ.] 0.1g 11 *1 E 20 HE Previous Code 20P2F-A NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. F 1 Index mark 10 c A1 Reference Symbol D A L *2 A2 *3 e bp y Detail F D E A2 A A1 bp c HE e y L Rev.2.
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R8C/14 Group, R8C/15 Group Appendix 2. Connecting Example between Serial Writer and On-Chip Debugging Appendix 2. Connecting Example between Serial Writer and On-Chip Debugging Emulator Appendix Figure 2.1 shows the Connecting Example with M16C Flash Starter (M3A-0806) and Appendix Figure 2.2 shows the Connecting Example with Emulator E8 (R0E000080KCE00).
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R8C/14 Group, R8C/15 Group Appendix 3. Example of Oscillation Evaluation Circuit Appendix 3. Example of Oscillation Evaluation Circuit Appendix Figure 3.1 shows the Example of Oscillation Evaluation Circuit. 20 2 19 3 18 4 Connect Oscillation Circuit VSS 5 6 7 8 R8C/14, R8C/15 Group RESET 1 Rev.2.10 Jan 19, 2006 REJ09B0164-0210 15 14 13 12 10 11 Example of Oscillation Evaluation Circuit Page 252 of 253 16 9 NOTES: 1. Set a program before evaluating. Appendix Figure 3.
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R8C/14 Group, R8C/15 Group Register Index Register Index A P U AD .......................................... 171 ADCON0 ................................. 170 ADCON1 ................................. 170 ADCON2 ................................. 171 ADIC ........................................ 61 AIER ......................................... 77 P1 ..........................................184 P3 ..........................................184 P4 ..........................................184 PD1 ........
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REVISION REVISION HISTORY HISTORY R8C/14 Group, R8C/15 Group Hardware Description Rev. Date 0.10 May 17, 2004 − First Edition issued 0.20 Jul 12, 2004 − Rev.0.20 issued 0.30 Aug 06, 2004 all pages 2 3 9 10 14,15 16 18 19 Page 20-25 26-35 37 40 41 42 44 47 48 52 60 61 62 68 72 74 75 80-84 87 89 90 91 92 93 94 95 97 98 99 100 105 107 Summary Words standardized (on-chip oscillator, serial interface, SSU) Table 1.1 revised Table 1.2 revised Table 1.5 revised Table 1.
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REVISION HISTORY Rev. Date 0.30 Aug 06, 2004 R8C/14 Group, R8C/15 Group Hardware Description Page Summary 110 112 114 118 119 121 123 125 130 131 136 138 140 141 143 144 146 148 152 154 159 162 164 165 167 171 174 175 176 178 179 180 184 185 186 188 89 190 191 193 195 Table 13.9 revised Figure 13.20 revised Table 13.10 revised Figure 13.25 revised Figure 13.26 revised Figure 13.28 revised Table 13.11 revised Table 13.12 revised Figure 14.4 revised Figure 14.5 revised 14.1.3 revised Table 14.
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REVISION HISTORY Rev. Date 1.00 Feb 25, 2005 R8C/14 Group, R8C/15 Group Hardware Description Page Summary 2-3 5 6 7-8 16 Tables 1.1 and 1.2 revised Table 1.3 and figure 1.2 revised Table 1.4 and figure 1.3 revised Figures 1.4 and 1.5 revised Tabel 4.1, The value after reset to 000XXXXXb to 00011111b at 000Fh; and the value after reset to 00001000b to 0000X000b and 01001001b to 0100X001b at 0036h revised 18 Tabel 4.
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REVISION HISTORY Rev. Date 1.00 Feb 25, 2005 R8C/14 Group, R8C/15 Group Hardware Description Summary Table 15.1 NOTE2 added Figure 15.4 NOTES added Figure 15.6 revised; The value after reset to 00h Figure 15.8 revised 15.2 revised; “15.2 SS Shift Register” added and 15.2 revised to 15.5.2 Figure 15.13 NOTE2 added Figure 15.14 revised 15.5.4 revised 15.6 revised Figure 15.17 revised 15.6.2 revised 15.6.4 revised Table 16.1 revised Figures 16.2, 16.4 and 16.5 revised 17.1, 17.2 and 17.
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REVISION HISTORY REVISION HISTORY Rev. Date 2.00 Jan 12, 2006 R8C/14 Group, R8C/15 Group Hardware R8C/14 Group, R8C/15 Group Hardware Description Page Summary 1 1. Overview; “20-pin plastic molded LSSOP or SDIP” → “20-pin plastic molded LSSOP” revised 2 Table 1.1 Performance Outline of the R8C/14 Group; Package: “20-pin plastic molded SDIP” deleted 3 Table 1.
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REVISION HISTORY Rev. Date 2.00 Jan 12, 2006 R8C/14 Group, R8C/15 Group Hardware Description Page Summary 32 Table 6.2 Setting Procedure of Voltage Monitor 1 Reset Associated Bit revised 33 Table 6.3 Setting Procedure of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Associated Bit revised 37 Table 8.2 Bus Cycles for Access Space of the R8C/15 Group added, Table 8.3 Access Unit and Bus Operation; “SFR” → “SFR, Data flash”, “ROM/RAM” → “ROM (Program ROM), RAM” revised 38 Table 9.
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REVISION HISTORY Rev. Date 2.00 Jan 12, 2006 R8C/14 Group, R8C/15 Group Hardware Description Page Summary 76 11.4 Address Match Interrupt; “... , do not use an address match interrupt in a user system.” → “... , do not set an address match interrupt (the registers of AIER, RMAD0, RMAD1 and the fixed vector tables) in a user system.” revised 77 Figure 11.19 AIER, RMAD0 to RMAD1 Registers; AIER Register revised 79 Figure 12.
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REVISION HISTORY Rev. Date 2.00 Jan 12, 2006 R8C/14 Group, R8C/15 Group Hardware Description Page Summary 103 Table 13.7 Specification of Timer Mode; “• When writing ... registers (the data is transferred to the counter when the following count source is input) while the TZWC bit is set to “0” (writing to the reload register and counter simultaneously).” → “• When writing ...
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REVISION HISTORY Rev. Date 2.00 Jan 12, 2006 R8C/14 Group, R8C/15 Group Hardware Description Page Summary 193 18.2 Memory Map; “The user ROM ... area ... Block A and B.” → “The user ROM ... area (program ROM) ... Block A and B (data flash).” revised Figure 18.1 Flash Memory Block Diagram for R8C/14 Group revised 194 Figure 18.2 Flash Memory Block Diagram for R8C/15 Group revised 196 Figure 18.4 OFS Register; NOTE1 revised, NOTE2 added 200 Figure 18.
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REVISION HISTORY Rev. Date 2.00 Jan 12, 2006 2.10 Jan 19, 2006 R8C/14 Group, R8C/15 Group Hardware Description Page Summary 228 Table 19.14 Electrical Characteristics (2) [Vcc = 5V] NOTE1 deleted 229 Table 19.18 Serial Interface; “35” → “50”, “80” → “50” 231 Table 19.20 Electrical Characteristics (3) [VCC = 3V] revised 232 Table 19.21 Electrical Characteristics (4) [Vcc = 3V] NOTE1 deleted 233 Table 19.25 Serial Interface; “55” → “70”, “160” → “80” 239 20.3.
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R8C/14 Group, R8C/15 Group Hardware Manual Publication Data : Rev.0.10 Rev.2.10 May 17, 2004 Jan 19, 2006 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2006. Renesas Technology Corp., All rights reserved.
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R8C/14 Group, R8C/15 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0164-0210