Datasheet
R01DS0064EJ0120 Rev.1.20 Page 15 of 109
Feb 6, 2013
R32C/117 Group 1. Overview
Figure 1.4 Pin Assignment for the 100-pin Package (top view)
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RXD4 / SCL4 / STXD4 / ADTRG / P9_7 P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT / MSDA
P6_7 / TXD1 / SDA1 / SRXD1AVCC
VREF
AN_0 / P10_0
AVSS
AN_1 / P10_1
AN_2 / P10_2
AN_3 / P10_3
KI0 / AN_4 / P10_4
KI1 / AN_5 / P10_5
KI2 / AN_6 / P10_6
KI3 / AN_7 / P10_7
AN0_0 / D0 / P0_0
AN0_1 / D1 / P0_1
AN0_2 / D2 / P0_2
AN0_3 / D3 / P0_3
AN0_4 / D4 / P0_4
AN0_5 / D5 / P0_5
AN0_6 / D6 / P0_6
AN0_7 / D7 / P0_7
P6_6 / RXD1 / SCL1 / STXD1
P6_5 / CLK1
P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2
P6_3 / TXD0 / SDA0 / SRXD0
P6_2 / TB2IN / RXD0 / SCL0 / STXD0
P6_1 / TB1IN / CLK0
P6_0 / TB0IN / CTS0 / RTS0 / SS0
P5_7 / RDY / CS3 / CTS7 / RTS7
P5_6 / ALE / CS2 / RXD7
P5_5 / HOLD / CLK7
P5_4 / HLDA / CS1 / TXD7
P5_3 / CLKOUT / BCLK
P5_2 / RD
P5_1 / WR1 / BC1
P5_0 / WR0 / WR
P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6
P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6
P4_5 / CS2 / A21 / CLK6
P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6
TXD4 / SDA4 / SRXD4 / ANEX1 / P9_6
CLK4 / ANEX0 / P9_5
CTS4 / RTS4 / SS4 / TB4IN / DA1 / P9_4
VDC0
P9_1
VDC1
NSD
CNVSS
XCIN / P8_7
XCOUT / P8_6
RESET
XOUT
VSS
XIN
VCC
NMI / P8_5
INT2 / P8_4
CAN0IN / CAN0WU / INT1 / P8_3
CAN0OUT / INT0 / P8_2
IIO1_5 / UD0B / UD1B / CTS5 / RTS5 / SS5 / U / TA4IN / P8_1
UD0A / UD1A / RXD5 / SCL5 / STXD5 / U / TA4OUT / P8_0
CAN0IN / CAN0WU / IIO1_4 / UD0B / UD1B / CLK5 / TA3IN / P7_7
CAN0OUT / IIO1_3 / UD0A / UD1A / CTS8 / RTS8 / TXD5 / SDA5 / SRXD5 / TA3OUT / P7_6
IIO1_2 / RXD8 / W / TA2IN / P7_5
IIO1_1 / CLK8 / W / TA2OUT / P7_4
IIO1_0 / TXD8 / CTS2 / RTS2 / SS2 / V / TA1IN / P7_3
P7_2 / TA1OUT / V / CLK2
P7_1 / TA0IN / TB5IN / RXD2 / SCL2 / STXD2 / IIO1_7 / OUTC2_2 / ISRXD2 / IEIN / MSCL
TB3IN / DA0 / P9_3
IIO0_1 / IIO1_1 / D9 / P1_1
IIO0_2 / IIO1_2 / D10 / P1_2
P1_3 / D11 / IIO0_3 / IIO1_3
P1_4 / D12 / IIO0_4 / IIO1_4
P1_5 / D13 / INT3 / IIO0_5 / IIO1_5
P1_6 / D14 / INT4 / IIO0_6 / IIO1_6
P1_7 / D15 / INT5 / IIO0_7 / IIO1_7
P2_0 / A0 / [A0/D0] / BC0 / [BC0/D0] / AN2_0
VSS
P3_0 / A8 / [A8/D8] / TA0OUT / UD0A / UD1A
VCC
P3_1 / A9 / [A9/D9] / TA3OUT / UD0B / UD1B
P3_2 / A10 / [A10/D10] / TA1OUT / V
P3_3 / A11 / [A11/D11] / TA1IN / V
P3_4 / A12 / [A12/D12] / TA2OUT / W
P3_5 / A13 / [A13/D13] / TA2IN / W
P3_6 / A14 / [A14/D14] / TA4OUT / U
P3_7 / A15 / [A15/D15] / TA4IN / U
P4_0 / A16 / CTS3 / RTS3 / SS3
P4_1 / A17 / CLK3
P4_2 / A18 / RXD3 / SCL3 / STXD3 / ISRXD2 / IEIN
P4_3 / A19 / TXD3 / SDA3 / SRXD3 / OUTC2_0 / ISTXD2 / IEOUT
P2_1 / A1 / [A1/D1] / AN2_1
P2_2 / A2 / [A2/D2] / AN2_2
P2_3 / A3 / [A3/D3] / AN2_3
P2_4 / A4 / [A4/D4] / AN2_4
P2_5 / A5 / [A5/D5] / AN2_5
P2_6 / A6 / [A6/D6] / AN2_6
P2_7 / A7 / [A7/D7] / AN2_7
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IIO0_0 / IIO1_0 / D8 / P1_0
PLQP0100KB-A
(100P6Q-A)
(Top view)
R32C/117 Group
(Note 1)
(Note 3)
(Note 2)
Notes:
1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins.
2. The following pins are 5 V tolerant inputs: P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, and P8_0 to P8_3.
3. The position of pin number 1 varies by product. Refer to the indexmark in attached “Package Dimensions”.