Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 16/32-Bit 50 MHz I/O number 84

R01DS0064EJ0120 Rev.1.20 Page 1 of 109

Feb 6, 2013

R32C/117 Group

RENESAS MCU

R01DS0064EJ0120

Rev.1.20

Feb 6, 2013

Datasheet

R32C/117 Group Datasheet

1. Overview

1.1 Features

The M16C Family offers a robust platform of 32-/16-bit CISC microcomputers (MCUs) featuring high ROM

code efficiency, extensive EMI/EMS noise immunity, ultra-low power consumption, high-speed processing

in actual applications, and numerous and varied integrated peripherals. Extensive device scalability from

low- to high-end, featuring a single architecture as well as compatible pin assignments and peripheral

functions, provides support for a vast range of application fields.

The R32C/100 Series is a high-end microcontroller series in the M16C Family. With a 4-Gbyte memory

space, it achieves maximum code efficiency and high-speed processing with 32-bit CISC architecture,

multiplier, multiply-accumulate unit, and floating point unit. The selection from the broadest choice of on-

chip peripheral devices — UART, CRC, DMAC, A/D and D/A converters, timers, I

C, and watchdog timer

enables to minimize external components.

The R32C/117 Group is the standard MCU within the R32C/100 Series. This product, provided as 100-pin

and 144-pin plastic molded LQFP packages, has nine channels of serial interface, one channel of multi-

master I

C-bus interface, and one channel of CAN module.

1.1.1 Applications

Car audio, audio, printer, office/industrial equipment, etc.

Summary of content (114 pages)

PAGE 1
R32C/117 Group Datasheet Datasheet R32C/117 Group RENESAS MCU 1. R01DS0064EJ0120 Rev.1.20 Feb 6, 2013 Overview 1.1 Features The M16C Family offers a robust platform of 32-/16-bit CISC microcomputers (MCUs) featuring high ROM code efficiency, extensive EMI/EMS noise immunity, ultra-low power consumption, high-speed processing in actual applications, and numerous and varied integrated peripherals.
PAGE 2
R32C/117 Group 1.1.2 1. Overview Performance Overview Tables 1.1 to 1.4 list the performance overview of the R32C/117 Group. Table 1.1 Performance Overview for the 144-pin Package (1/2) Unit CPU Function Central processing unit Memory Explanation R32C/100 Series CPU Core • Basic instructions: 108 • Minimum instruction execution time: 15.
PAGE 3
R32C/117 Group Table 1.2 1.
PAGE 4
R32C/117 Group Table 1.3 1. Overview Performance Overview for the 100-pin Package (1/2) Unit CPU Function Central processing unit Memory Explanation R32C/100 Series CPU Core • Basic instructions: 108 • Minimum instruction execution time: 15.
PAGE 5
R32C/117 Group Table 1.4 1.
PAGE 6
R32C/117 Group 1.2 1. Overview Product Information Tables 1.5 and 1.6 list the product information and Figure 1.1 shows the details of the part number. Table 1.
PAGE 7
R32C/117 Group Table 1.6 1.
PAGE 8
R32C/117 Group 1.
PAGE 9
R32C/117 Group 1.3 1. Overview Block Diagram Figure 1.2 shows the block diagram for the R32C/117 Group.
PAGE 10
R32C/117 Group 1.4 1.
PAGE 11
R32C/117 Group Table 1.7 Pin No. Control Pin 1.
PAGE 12
R32C/117 Group Table 1.8 Pin No. Control Pin 1.
PAGE 13
R32C/117 Group Table 1.9 Pin No. Control Pin 75 76 1.
PAGE 14
R32C/117 Group Table 1.10 Pin No. Control Pin 1.
PAGE 15
R32C/117 Group 1.
PAGE 16
R32C/117 Group Table 1.11 Pin No. Control Pin 1.
PAGE 17
R32C/117 Group Table 1.12 Pin No. Control Pin 1.
PAGE 18
R32C/117 Group Table 1.13 Pin No. Control Pin 1.
PAGE 19
R32C/117 Group 1.5 1. Overview Pin Definitions and Functions Tables 1.14 to 1.18 list the pin definitions and functions. Table 1.14 Pin Definitions and Functions (1/4) Function Symbol Power supply VCC, VSS Connecting pins for decoupling capacitor VDC0, VDC1 Analog power supply AVCC, AVSS Reset input I/O Description I Applicable as follows: VCC = 3.0 to 5.
PAGE 20
R32C/117 Group Table 1.15 1. Overview Pin Definitions and Functions (2/4) Function Bus control pins Symbol I/O BC0/D0, BC2/D1 (1) CS0 to CS3 Description I/O Output of byte control (BC0 and BC2) and input/output of data (D0 and D1) by time-division while accessing an external memory space with multiplexed bus O Chip select output WR0/WR1/WR2/ WR3, WR/BC0/BC1/ BC2/BC3, RD (1) Output of write, byte control, and read signals. Either WRx or WR and BCx can be selected by a program.
PAGE 21
R32C/117 Group Table 1.16 1. Overview Pin Definitions and Functions (3/4) Function I/O port (1, 2) Input port (2) Timer A Symbol P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_3 to P14_6, P15_0 to P15_7 P9_1 (for 100-pin package) P14_1 (for 144pin package) TA0OUT to TA4OUT I/O Description I/O ports in CMOS.
PAGE 22
R32C/117 Group Table 1.17 1.
PAGE 23
R32C/117 Group Table 1.18 1.
PAGE 24
R32C/117 Group 2. 2. Central Processing Unit (CPU) Central Processing Unit (CPU) The CPU contains the registers shown below. There are two register banks each consisting of registers R2R0, R3R1, R6R4, R7R5, A0 to A3, SB, and FB.
PAGE 25
R32C/117 Group 2.1 2. Central Processing Unit (CPU) General Purpose Registers 2.1.1 Data Registers (R2R0, R3R1, R6R4, and R7R5) These 32-bit registers are primarily used for transfers and arithmetic/logic operations. Each of the registers can be divided into upper and lower 16-bit registers, e.g. R2R0 can be divided into R2 and R0, R3R1 can be divided into R3 and R1, etc.
PAGE 26
R32C/117 Group 2.1.8.5 2. Central Processing Unit (CPU) Register Bank Select Flag (B flag) This flag selects a register bank. It indicates 0 when register bank 0 is selected, and 1 when register bank 1 is selected. 2.1.8.6 Overflow Flag (O flag) This flag becomes 1 when the result of an operation overflows; otherwise it is 0. 2.1.8.7 Interrupt Enable Flag (I flag) This flag enables maskable interrupts. To disable maskable interrupts, set this flag to 0. To enable them, set this flag to 1.
PAGE 27
R32C/117 Group 2.2 2. Central Processing Unit (CPU) Fast Interrupt Registers The following three registers are provided to minimize the overhead of the interrupt sequence. 2.2.1 Save Flag Register (SVF) This 32-bit register is used to save the flag register when a fast interrupt occurs. 2.2.2 Save PC Register (SVP) This 32-bit register is used to save the program counter when a fast interrupt occurs. 2.2.
PAGE 28
R32C/117 Group 3. 3. Memory Memory Figure 3.1 shows the memory map of the R32C/117 Group. The R32C/117 Group provides a 4-Gbyte address space from 00000000h to FFFFFFFFh. The internal ROM is mapped from address FFFFFFFFh in the inferior direction. For example, the 1-Mbyte internal ROM is mapped from FFF00000h to FFFFFFFFh. The fixed interrupt vector table contains the start address of interrupt handlers and is mapped from FFFFFFDCh to FFFFFFFFh.
PAGE 29
R32C/117 Group 4. 4. Special Function Registers (SFRs) Special Function Registers (SFRs) SFRs are memory-mapped peripheral registers that control the operation of peripherals. Table 4.1 SFR List (1) to Table 4.39 SFR List (39) list the SFR details. Table 4.
PAGE 30
R32C/117 Group Table 4.2 4.
PAGE 31
R32C/117 Group Table 4.3 4.
PAGE 32
R32C/117 Group Table 4.4 4.
PAGE 33
R32C/117 Group Table 4.5 4.
PAGE 34
R32C/117 Group Table 4.6 4.
PAGE 35
R32C/117 Group Table 4.7 4.
PAGE 36
R32C/117 Group Table 4.8 4.
PAGE 37
R32C/117 Group Table 4.9 4.
PAGE 38
R32C/117 Group Table 4.10 4.
PAGE 39
R32C/117 Group Table 4.11 4.
PAGE 40
R32C/117 Group Table 4.12 4.
PAGE 41
R32C/117 Group Table 4.13 4.
PAGE 42
R32C/117 Group Table 4.14 4.
PAGE 43
R32C/117 Group Table 4.15 4.
PAGE 44
R32C/117 Group Table 4.16 4.
PAGE 45
R32C/117 Group Table 4.17 4.
PAGE 46
R32C/117 Group Table 4.18 4.
PAGE 47
R32C/117 Group Table 4.19 4.
PAGE 48
R32C/117 Group Table 4.20 4.
PAGE 49
R32C/117 Group Table 4.21 4.
PAGE 50
R32C/117 Group Table 4.22 4.
PAGE 51
R32C/117 Group Table 4.23 4. Special Function Registers (SFRs) SFR List (23) Address Register 040120h to 04403Fh 044040h 044041h 044042h 044043h 044044h 044045h 044046h 044047h 044048h 044049h 04404Ah 04404Bh 04404Ch 04404Dh 04404Eh Watchdog Timer Start Register 04404Fh Watchdog Timer Control Register 044050h 044051h 044052h 044053h 044054h 044055h 044056h 044057h 044058h 044059h 04405Ah 04405Bh 04405Ch 04405Dh 04405Eh 04405Fh Protect Register 2 X: Undefined Blanks are reserved. No access is allowed.
PAGE 52
R32C/117 Group Table 4.24 4.
PAGE 53
R32C/117 Group Table 4.25 4.
PAGE 54
R32C/117 Group Table 4.26 4.
PAGE 55
R32C/117 Group Table 4.27 4.
PAGE 56
R32C/117 Group Table 4.28 4.
PAGE 57
R32C/117 Group Table 4.29 4.
PAGE 58
R32C/117 Group Table 4.30 4.
PAGE 59
R32C/117 Group Table 4.31 4.
PAGE 60
R32C/117 Group Table 4.32 4.
PAGE 61
R32C/117 Group Table 4.33 4.
PAGE 62
R32C/117 Group Table 4.34 4.
PAGE 63
R32C/117 Group Table 4.35 4.
PAGE 64
R32C/117 Group Table 4.36 4.
PAGE 65
R32C/117 Group Table 4.37 4.
PAGE 66
R32C/117 Group Table 4.38 4.
PAGE 67
R32C/117 Group Table 4.39 4.
PAGE 68
R32C/117 Group 5. 5. Electrical Characteristics Electrical Characteristics Table 5.1 Absolute Maximum Ratings (1) Symbol Characteristic Condition Value Unit VCC Supply voltage VCC = AVCC -0.3 to 6.0 V AVCC Analog supply voltage VCC = AVCC -0.3 to 6.0 V VI Input voltage -0.3 to VCC + 0.3 V -0.3 to 6.0 V -0.3 to VCC + 0.
PAGE 69
R32C/117 Group Table 5.2 5. Electrical Characteristics Operating Conditions (1/5) (1) Symbol Characteristic Value Min. Typ. Max. 3.0 5.0 5.5 Unit VCC Digital supply voltage AVCC Analog supply voltage VREF Reference voltage VSS Digital ground voltage 0 V AVSS Analog ground voltage 0 V dVCC/dt VCC ramp up rate (VCC < 2.0 V) VIH High level input voltage VCC V VCC 3.0 V 0.05 V V/ms XIN, RESET, CNVSS, NSD, P2_0 to P2_7, P3_0 to P3_7, P5_0 to P5_3, P8_4 to P8_7 (2), 0.
PAGE 70
R32C/117 Group Table 5.3 5. Electrical Characteristics Operating Conditions (2/5) (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1) Symbol CVDC Value (2) Characteristic Decoupling capacitance for voltage regulator Min. Typ. Max. Inter-pin voltage: 1.5 V 2.4 10.0 Unit µF Notes: 1. The device is operationally guaranteed under these operating conditions. 2.
PAGE 71
R32C/117 Group Table 5.4 5. Electrical Characteristics Operating Conditions (3/5) (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1) Symbol Characteristic Value Min. Typ. Max.
PAGE 72
R32C/117 Group Table 5.5 5. Electrical Characteristics Operating Conditions (4/5) (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1) Symbol Value Characteristic Min. Typ. Max.
PAGE 73
R32C/117 Group Table 5.6 5. Electrical Characteristics Operating Conditions (5/5) (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1) Symbol Vr(VCC) Allowable ripple voltage dVr(VCC)/dt Ripple voltage gradient fr(VCC) Value Characteristic Min. Typ. Max. Unit VCC = 5.0 V 0.5 Vp-p VCC = 3.0 V 0.3 Vp-p VCC = 5.0 V ±0.3 V/ms VCC = 3.0 V ±0.3 V/ms 10 kHz Allowable ripple frequency Note: 1. The device is operationally guaranteed under these operating conditions.
PAGE 74
R32C/117 Group Table 5.7 5. Electrical Characteristics Electrical Characteristics of RAM (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Symbol VRDR Table 5.8 Characteristic RAM data retention voltage — — — — In stop mode Value Min. Typ. Max. 2.0 Unit V Electrical Characteristics of Flash Memory (VCC = 3.0 to 5.
PAGE 75
R32C/117 Group Table 5.9 5. Electrical Characteristics Power Supply Circuit Timing Characteristics (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Symbol Measurement Condition Characteristic Value Min. Typ. Max.
PAGE 76
R32C/117 Group Table 5.12 5. Electrical Characteristics Electrical Characteristics of Oscillator (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Symbol Measurement Condition Characteristics fSO(PLL) PLL clock self-oscillation frequency tLOCK(PLL) PLL lock time (1) tjitter(p-p) PLL jitter period (p-p) f(OCO) On-chip oscillator frequency Value Unit Min. Typ. Max. 35 50 65 MHz 1 ms 2.0 ns 250 kHz 62.5 125 Note: 1.
PAGE 77
R32C/117 Group 5. Electrical Characteristics Timing Requirements (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.14 Flash Memory CPU Rewrite Mode Timing Symbol Value Characteristics Min. Max.
PAGE 78
R32C/117 Group 5. Electrical Characteristics VCC = 5 V Table 5.15 Electrical Characteristics (1/3) (VCC = 4.2 to 5.5 V, VSS = 0 V, Ta = Topr, and f(CPU) = 64 MHz, unless otherwise noted) VOH Min. IOH = -5 mA VCC - 2.0 VCC V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, IOH = -200 µA VCC - 0.
PAGE 79
R32C/117 Group 5. Electrical Characteristics VCC = 5 V Table 5.16 Electrical Characteristics (2/3) (VCC = 4.2 to 5.5 V, VSS = 0 V, Ta = Topr, and f(CPU) = 64 MHz, unless otherwise noted) Symbol Characteristic Value Measurement Unit Condition Min. Typ. Max.
PAGE 80
R32C/117 Group 5. Electrical Characteristics VCC = 5 V Table 5.17 Symbol ICC Electrical Characteristics (3/3) (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Characterist ic Measurement Condition Power supply In single-chip mode, current output pins are left open and others are connected to VSS XIN-XOUT Drive strength: low XCIN-XCOUT Drive strength: low R01DS0064EJ0120 Rev.1.
PAGE 81
R32C/117 Group 5. Electrical Characteristics VCC = 5 V Table 5.18 Symbol — A/D Conversion Characteristics (VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, Ta = Topr, and f(BCLK) = 32 MHz, unless otherwise noted) Characteristic Measurement Condition Resolution VREF = VCC Absolute error VREF = VCC = 5 V Value Min. Typ. Max.
PAGE 82
R32C/117 Group 5. Electrical Characteristics VCC = 5 V Table 5.19 Symbol D/A Conversion Characteristics (VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, and Ta = Topr, unless otherwise noted) Characteristic — Resolution — Absolute precision tS Settling time RO Output resistance IVREF Reference input current Measurement Condition Value Min. 4 See Note 1 Typ. 10 Max. Unit 8 Bits 1.0 % 3 µs 20 k 1.5 mA Note: 1. One D/A converter is used.
PAGE 83
R32C/117 Group 5. Electrical Characteristics VCC = 5 V Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.20 External Clock Input Symbol Value Characteristic Min. Max. 62.
PAGE 84
R32C/117 Group 5. Electrical Characteristics VCC = 5 V Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.22 Timer A Input (counting input in event counter mode) Symbol Characteristic Value Min. Max. Unit tc(TA) TAiIN input clock cycle time 200 ns tw(TAH) TAiIN input high level pulse width 80 ns tw(TAL) TAiIN input low level pulse width 80 ns Table 5.23 Timer A Input (gating input in timer mode) Symbol Characteristic Value Min. Max.
PAGE 85
R32C/117 Group 5. Electrical Characteristics VCC = 5 V Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.27 Timer B Input (counting input in event counter mode) Symbol Characteristic Value Min. Max.
PAGE 86
R32C/117 Group 5. Electrical Characteristics VCC = 5 V Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.30 Serial Interface Symbol Characteristic Value Min. Max. Unit tc(CK) CLKi input clock cycle time 200 ns tw(CKH) CLKi input high level pulse width 80 ns tw(CKL) CLKi input low level pulse width 80 ns tsu(D-C) RXDi input setup time 80 ns th(C-D) RXDi input hold time 90 ns Table 5.
PAGE 87
R32C/117 Group 5. Electrical Characteristics VCC = 5 V Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.34 Multi-master I2C-bus Interface Value Symbol Characteristic Standard-mode Min. Max. Fast-mode Min. Unit Max.
PAGE 88
R32C/117 Group 5. Electrical Characteristics VCC = 5 V Switching Characteristics (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.35 Symbol External Bus Timing (separate bus) Characteristic tsu(S-R) Chip-select setup time before read th(R-S) Measurement Condition Value Min. Max.
PAGE 89
R32C/117 Group 5. Electrical Characteristics VCC = 5 V Switching Characteristics (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.36 Symbol External Bus Timing (multiplexed bus) Characteristic tsu(S-ALE) Chip-select setup time before ALE th(R-S) Measurement Condition Value Min. Max. Unit (1) ns Chip-select hold time after read 1.5 × tc(Base) - 15 ns tsu(A-ALE) Address setup time before ALE (1) ns th(ALE-A) Address hold time after ALE 0.
PAGE 90
R32C/117 Group 5. Electrical Characteristics VCC = 5 V Switching Characteristics (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.37 Serial Interface Symbol td(C-Q) TXDi output delay time th(C-Q) TXDi output hold time Table 5.38 Min. Max. Unit 80 Refer to Figure 5.6 Measurement Condition Characteristic td(ISCLK2-TXD) ISTXD2 output delay time th(ISCLK2-RXD) ISTXD2 output hold time Symbol Value ns 0 ns Intelligent I/O Symbol Table 5.
PAGE 91
R32C/117 Group 5. Electrical Characteristics VCC = 3.3 V Table 5.41 Electrical Characteristics (1/3) (VCC = 3.0 to 3.6 V, VSS = 0 V, Ta = Topr, and f(CPU) = 64 MHz, unless otherwise noted) Symbol VOH VOL Characteristic Value Measurement Condition Min. VCC - 0.
PAGE 92
R32C/117 Group 5. Electrical Characteristics VCC = 3.3 V Table 5.42 Electrical Characteristics (2/3) (VCC = 3.0 to 3.
PAGE 93
R32C/117 Group 5. Electrical Characteristics VCC = 3.3 V Table 5.43 Symbol ICC Electrical Characteristics (3/3) (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Characte ristic Power supply current Measurement Condition Value Min. Typ. Max.
PAGE 94
R32C/117 Group 5. Electrical Characteristics VCC = 3.3 V Table 5.44 Symbol — A/D Conversion Characteristics (VCC = AVCC = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V, Ta = Topr, and f(BCLK) = 32 MHz, unless otherwise noted) Characteristic Measurement Condition Value Min. Unit VREF = VCC 10 Bits Absolute error VREF = VCC = 3.
PAGE 95
R32C/117 Group 5. Electrical Characteristics VCC = 3.3 V Table 5.45 Symbol D/A Conversion Characteristics (VCC = AVCC = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V, and Ta = Topr, unless otherwise noted) Characteristic — Resolution — Absolute precision tS Settling time RO Output resistance IVREF Reference input current Measurement Condition Value Min. 4 See Note 1 Typ. 10 Max. Unit 8 Bits 1.0 % 3 µs 20 k 1.0 mA Note: 1. One D/A converter is used.
PAGE 96
R32C/117 Group 5. Electrical Characteristics VCC = 3.3 V Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.46 External Clock Input Symbol Value Characteristic Min. Max. 62.
PAGE 97
R32C/117 Group 5. Electrical Characteristics VCC = 3.3 V Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.48 Timer A Input (counting input in event counter mode) Symbol Characteristic Value Min. Max. Unit tc(TA) TAiIN input clock cycle time 200 ns tw(TAH) TAiIN input high level pulse width 80 ns tw(TAL) TAiIN input low level pulse width 80 ns Table 5.49 Timer A Input (gating input in timer mode) Symbol Characteristic Value Min. Max.
PAGE 98
R32C/117 Group 5. Electrical Characteristics VCC = 3.3 V Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.53 Timer B Input (counting input in event counter mode) Symbol Characteristic Value Min. Max.
PAGE 99
R32C/117 Group 5. Electrical Characteristics VCC = 3.3 V Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.56 Serial Interface Symbol Characteristic Value Min. Max. Unit tc(CK) CLKi input clock cycle time 200 ns tw(CKH) CLKi input high level pulse width 80 ns tw(CKL) CLKi input low level pulse width 80 ns tsu(D-C) RXDi input setup time 80 ns th(C-D) RXDi input hold time 90 ns Table 5.
PAGE 100
R32C/117 Group 5. Electrical Characteristics VCC = 3.3 V Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.60 Multi-master I2C-bus Interface Value Symbol Characteristic Standard-mode Min. Max. 600 Fast-mode Min. Max.
PAGE 101
R32C/117 Group 5. Electrical Characteristics VCC = 3.3 V Switching Characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.61 Symbol External Bus Timing (separate bus) Characteristic tsu(S-R) Chip-select setup time before read th(R-S) Measurement Condition Value Min. Max.
PAGE 102
R32C/117 Group 5. Electrical Characteristics VCC = 3.3 V Switching Characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.62 Symbol External Bus Timing (multiplexed bus) Characteristic tsu(S-ALE) Chip-select setup time before ALE th(R-S) Measurement Condition Value Min. Max. Unit (1) ns Chip-select hold time after read 1.5 × tc(Base) - 15 ns tsu(A-ALE) Address setup time before ALE (1) ns th(ALE-A) Address hold time after ALE 0.
PAGE 103
R32C/117 Group 5. Electrical Characteristics VCC = 3.3 V Switching Characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.63 Serial Interface Symbol td(C-Q) TXDi output delay time th(C-Q) TXDi output hold time Table 5.64 Intelligent I/O Symbol ISTXD2 output delay time th(ISCLK2-RXD) ISTXD2 output hold time Symbol Value Min. Measurement Condition Max. 80 Refer to Figure 5.6 Characteristic td(ISCLK2-TXD) Table 5.
PAGE 104
R32C/117 Group 5. Electrical Characteristics MCU Pin to be measured 30 pF Figure 5.6 Switching Characteristic Measurement Circuit t c(X) XIN t w(XH) t r(X) Figure 5.7 t w(XL) t f(X) External Clock Input Timing R01DS0064EJ0120 Rev.1.
PAGE 105
R32C/117 Group 5. Electrical Characteristics External bus timing (separate bus) Read cycle t cR t su(S-R) t h(R-S) t su(A-R) t h(R-A) CS0 to CS3 A23 to A0, BC0 to BC3 t w(R) RD t su(D-R) t h(R-D) D31 to D0 Write cycle t cW t su(S-W) t h(W-S) t su(A-W) t h(W-A) CS0 to CS3 A23 to A0, BC0 to BC3 t w(W) WR, WR0 to WR3 t su(D-W) t h(W-D) D31 to D0 Measurement conditions Item Figure 5.8 V CC = 4.2 to 5.5 V V CC = 3.0 to 3.6 V Criterion for input voltage VIH 2.5 V 1.5 V VIL 0.8 V 0.
PAGE 106
R32C/117 Group 5.
PAGE 107
R32C/117 Group 5.
PAGE 108
R32C/117 Group 5. Electrical Characteristics t c(SCL) MSCL t w(SCLH) t w(SCLL) t r(SCL) t f(SCL) t r(SDA) t f(SDA) MSDA t w(SDAH)P t h(SDA-SCL)S t su(SCL-SDA)P t su(SCL-SDA)P MSCL MSDA (input) t h(SDA-SCL)S t d(SDA-SCL)S t d(SCL-SDA)P t d(SCL-SDA)P MSCL MSDA (output) t d(SDA-SCL)S t su(SDA-SCL) t h(SCL-SDA) MSCL MSDA (input) t d(SCL-SDA) MSCL MSDA (output) Figure 5.11 Timing of Multi-master I2C-bus Interface R01DS0064EJ0120 Rev.1.
PAGE 109
R32C/117 Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A / FP-144L / FP-144LV MASS[Typ.] 1.2g HD *1 D 108 73 109 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 72 bp c Reference Dimension in Millimeters Symbol *2 E HE c1 b1 Terminal cross section Index mark c 36 A 1 ZD ZE 37 A2 144 F A1 S Min Nom Max 19.
PAGE 110
Revision History Rev. Date 1.00 1.01 Nov 19, 2009 Mar 11, 2010 1.10 Jun 23, 2010 Page — — — — — 3, 5 6 11 21 36, 39 41 43 54 69 79 1.
PAGE 111
Revision History Rev. Date R32C/117 Group Datasheet Description Summary Page — 2, 4 6 6, 7 10, 15 11, 16 21 23 — 25 — Chapter 1. Overview • Modified wording and enhanced description in this chapter • Modified expressions “Main clock oscillator stop/re-oscillation detection”, “calculation transfer”, “chained transfer”, and “inputs/ outputs” in Tables 1.1 and 1.
PAGE 112
Revision History Rev. Date Page 87, 90, 100, 103 R32C/117 Group Datasheet Description Summary • Changed expression “restart condition” in Tables 5.34, 5.39, 5.40, 5.60, 5.65, and 5.66 to “repeated START condition” All trademarks and registered trademarks are the property of their respective owners.
PAGE 113
General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
PAGE 114
Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2.