Datasheet

A- 2
10, 15 • Changed order of signals in
Figures 1.3 and 1.4
11, 16 • Changed order of timer pins “TB5IN/TA0IN” in Tables 1.7 and 1.11 to
“TA0IN/TB5IN”
21
• Changed expression “I
2
C bus” in Table 1.16 to “I
2
C-bus”
23 • Modified Note 1 of
Table 1.18
Chapter 2. CPU
— • Modified wording and enhanced description in this chapter
25 • Corrected a typo “R3R0” in line 3 of
2.1.1 to “R3R1”
Chapter 3. Memory
— • Modified wording and enhanced description in this chapter
Chapter 4. SFRs
—
• Changed expressions “I
2
C Bus” and “I
2
C-Bus” to “I
2
C-bus”
34, 35, 37 • Changed hexadecimal format of reset values for registers G1BCR0,
G2BCR0, and G0BCR0 in
Tables 4.6, 4.7, and 4.9 to binary
41 • Changed register name “Increment/Decrement Counting Select
Register” in
Table 4.13 to “Increment/Decrement Select Register”
43 • Corrected reset value “X00X X000b” for AD0CON2 register in
Table
4.15
to “XX0X X000b”
53 • Modified register name “I
2
C Bus START Condition/STOP Condition
Control Register” in
Table 4.25 to “I
2
C-bus START and STOP
Conditions Control Register”; Corrected reset values for the following
registers in: I2CSSCR, I2CCR1, I2CCR2, I2CSR, and I2CMR
Chapter 5. Electrical Characteristics
— • Modified wording and enhanced description in this chapter
60 • Changed expression “Programming and erasure endurance of flash
memory” in
Table 5.8 to “Program/erase cycles”; Changed its unit
“times” to “Cycles”
65, 78 • Added “MSCL” and “MSDA” to
Tables 5.16 and 5.42
66, 79 • Modified description “Drive power” in Tables 5.17 and 5.43 to “Drive
strength”
72, 85 • Corrected “INTi” in the title of
Tables 5.32 and 5.58 to “INTi”
73, 76,
86, 89
• Changed expression “restart condition” in
Tables 5.34, 5.39, 5.40,
5.60, 5.65, and 5.66
to “repeated START condition”
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Revision History R32C/116 Group Datasheet
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