Datasheet

R01DS0063EJ0120 Rev.1.20 Page 24 of 95
Feb 6, 2013
R32C/116 Group 2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
The CPU contains the registers shown below. There are two register banks each consisting of registers
R2R0, R3R1, R6R4, R7R5, A0 to A3, SB, and FB.
Figure 2.1 CPU Registers
DDA0
DDR0
DSA0
DSR0
DDA0
DCR0
DCT0
DMD0
DDR0
DSA0
DSR0
DDA0
DCR0
DCT0
DMD0
DDR0
DSA0
DSR0
DDA0
DCR0
DCT0
DMD0
DDR0
DSA0
DSR0
DCR0
DCT0
DMD0
b0b31
VCT
SVP
SVF
PC
INTB
USP
ISP
FB
SB
A3
A2
A1
R5R7
R6 R4
R1LR1HR3LR3H
R2H R2L R0H R0L
A0
FLG
b0b31
General purpose
registers
Fast interrupt
registers
DMAC-associated
registers
(2)
Notes:
1.There are two banks of these registers.
2.There are four identical sets of DMAC-associated registers.
DMA destination address reload register
Flag register
Data registers
(1)
Address registers
(1)
Static base register
(1)
Frame base register
(1)
User stack pointer
Interrupt stack pointer
Interrupt vector table base register
Program counter
Save flag register
Save PC register
Vector register
R2R0
R3R1
R6R4
R7R5
DMA source address register
DMA source address reload register
DMA terminal count reload register
DMA terminal count register
DMA mode register
CDZSBOIUIPLRND
b0b31 b8 b7b16 b15
b0b31
b23 b15 b7
DMA destination address register
Blank spaces are reserved.
FU
FO
DP
b24 b23
b23