Datasheet

R01DS0098EJ0180 Rev.1.80 Page 20 of 208
May 13, 2014
RX63N Group, RX631 Group 1. Overview
Bus control RD# Output Strobe signal which indicates that reading from the external bus
interface space is in progress.
WR# Output Strobe signal which indicates that writing to the external bus
interface space is in progress, in 1-write strobe mode.
WR0# to WR3# Output Strobe signals which indicate that either group of data bus pins
(D7 to D0, D15 to D8, D23 to D16, and D31 to D24) is valid in
writing to the external bus interface space, in byte strobe mode.
BC0# to BC3# Output Strobe signals which indicate that either group of data bus pins
(D7 to D0, D15 to D8, D23 to D16, and D31 to D24) is valid in
access to the external bus interface space, in 1-write strobe
mode.
ALE Output Address latch signal when address/data multiplexed bus is
selected.
CKE Output Output pin for SDRAM clock enable signals.
SDCS# Output Output pin for SDRAM chip select signals.
RAS# Output Output pin for SDRAM row address strobe signals.
CAS# Output Output pin for SDRAM column address strobe signals.
WE# Output Output pin for SDRAM write enable signals.
DQM0 to DQM3 Output Output pins for SDRAM I/O data mask enable signals.
CS0# to CS7# Output Select signals for CS area.
WAIT# Input Input pins for wait request signals in access to the external
space.
EXDMA controller EDREQ0, EDREQ1 Input pins for external DMA transfer requests.
EDACK0, EDACK1 Output pins for single address transfer acknowledge signals.
Interrupt NMI Input Non-maskable interrupt request signal.
IRQ0 to IRQ15 Input Maskable interrupt request signals.
Multi-function timer pulse
unit 2
MTIOC0A, MTIOC0B
MTIOC0C, MTIOC0D
I/O The TGRA0 to TGRD0 input capture input/output compare
output/PWM output pins.
MTIOC1A, MTIOC1B I/O The TGRA1 and TGRB1 input capture input/output compare
output/PWM output pins.
MTIOC2A, MTIOC2B I/O The TGRA2 and TGRB2 input capture input/output compare
output/PWM output pins.
MTIOC3A, MTIOC3B
MTIOC3C, MTIOC3D
I/O The TGRA3 to TGRD3 input capture input/output compare
output/PWM output pins.
MTIOC4A, MTIOC4B
MTIOC4C, MTIOC4D
I/O The TGRA4 to TGRD4 input capture input/output compare
output/PWM output pins.
MTIC5U, MTIC5V
MTIC5W
Input The TGRU5, TGRV5, and TGRW5 input capture input/dead
time compensation input pins.
MTCLKA, MTCLKB
MTCLKC, MTCLKD
Input Input pins for external clock signals.
Port output enable 2 POE0# to POE3#
POE8#
Input Input pins for request signals to place the MTU large-current
pins in the high impedance state.
Table 1.4 Pin Functions (2/6)
Classifications Pin Name I/O Description