Datasheet

R01DS0098EJ0180 Rev.1.80 Page 185 of 208
May 13, 2014
RX63N Group, RX631 Group 5. Electrical Characteristics
5.8 Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Note: The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V
POR
, V
det1,
and V
det2
for the POR/ LVD.
Figure 5.63 Power-on Reset Timing
Table 5.33 Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Conditions: VCC = AVCC0 = VREFH = VCC_USB = V
BATT
= 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
T
a
= T
opr
Item Symbol Min. Typ. Max. Unit Test Conditions
Voltage detection
level
Power-on reset
(POR)
Low power
consumption
function disabled
V
POR
2.5 2.6 2.7 V Figure 5.63
Low power
consumption
function enabled
2.0 2.35 2.7
Voltage detection circuit (LVD0) V
det0
2.7 2.80 2.9 Figure 5.64
Voltage detection circuit (LVD1) V
det1_A
2.75 2.95 3.15 Figure 5.65
Voltage detection circuit (LVD2) V
det2_A
2.75 2.95 3.15 Figure 5.66
Internal reset time Power-on reset time t
POR
— 4.6 — ms Figure 5.63
LVD0 reset time t
LVD0
— 4.6 — Figure 5.64
LVD1 reset time t
LVD1
— 0.9 — Figure 5.65
LVD2 reset time t
LVD2
— 0.9 — Figure 5.66
Minimum VCC down time t
VOFF
200 — — µs Figure 5.63 and
Figure 5.64
Response delay time t
det
— — 200 µs Figure 5.63 to
Figure 5.66
LVD operation stabilization time (after LVD is enabled) Td
(E-A)
— — 3 µs Figure 5.65 and
Figure 5.66
Hysteresis width (LVD1 and LVD2) V
LVH
—80—mV
Internal reset signal
(active-low)
VCC
t
VOFF
t
det
t
POR
t
det
t
POR
t
det
V
POR