Datasheet

R01DS0098EJ0180 Rev.1.80 Page 18 of 208
May 13, 2014
RX63N Group, RX631 Group 1. Overview
1.3 Block Diagram
Figure 1.2 shows a block diagram.
Figure 1.2 Block Diagram
PDC
ETHERC : Ethernet controller
EDMAC : DMA controller for Ethernet controller
ICUb : Interrupt controller
DTCa : Data transfer controller
DMACA : DMA controller
EXDMACa : EXDMA controller
BSC : Bus controller
WDTA : Watchdog timer
IWDTa : Independent watchdog timer
CRC : CRC (cyclic redundancy check) calculator
SCIc, SCId : Serial communications interface
MPU : Memory protection unit
RSPI : Serial peripheral interface
CAN : CAN module
MTU2a : Multi-function timer pulse unit 2
POE2a : Port output enable 2
TPUa : 16-bit timer pulse unit
PPG : Programmable pulse generator
TMR : 8-bit timer
CMT : Compare match timer
RTCa : Realtime clock
RIIC : I
2
C bus interface
IEB : IEBus controller
DEU : Data encryption unit
PDC : Parallel data capture unit
External bus
BSC
Operand bus
Instruction bus
Internal main bus 1
Clock
generati
on circuit
RX CPU
RAM
ROM
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port C
10-bit ADC × 8 ch
12-bit ADC × 21 ch
MTU2a × 6 ch
10-bit DAC × 2 ch
RIIC × 4ch
USB 2.0 function module
CAN × 3 ch
RTCa
POE2a
TPUa × 6 ch (unit 1)
IEB
CMT × 2 ch (unit 1)
CMT × 2 ch (unit 0)
TMR × 2 ch (unit 1)
TMR × 2 ch (unit 0)
PPG (unit 1)
PPG (unit 0)
RSPI (unit 1)
RSPI (unit 0)
Internal main bus 2
DTCa
DMACA ×
4ch
ICUb
Temperature sensor
TPUa × 6 ch (unit 0)
RSPI (unit 2)
USB 2.0 host/function module
Port D
Port E
Port F
Port G
Port H
Port J
EDMAC
ETHERC
EXDMACa
Internal peripheral buses 1 to 6
SCIc × 12 ch
WDTA
E2 Data Flash
CRC
IWDTa
SCId × 1 ch
MPU
DEU